DS90UB913Q, DS90UB914Q
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SNLS420B –JULY 2012–REVISED APRIL 2013
Serializer A
DS90UB913Q
Camera A
DS90UB914Q
CMOS
Image
Sensor
DATA
PCLK
DATA
PCLK
FSYNC
FSYNC
2
2
I C
I C
Serializer B
DS90UB913Q
ECU
Module
Deserializer A
Camera B
CMOS
Image
Sensor
DATA
PCLK
FSYNC
2
I C
mC
Serializer B
Figure 28. Using the multiplexer on the Deserializer to enable a two camera system
Serial Frame Format
The High Speed Forward Channel is composed of 28 bits of data containing video data, sync signals, I2C and
parity bits. This data payload is optimized for signal transmission over an AC coupled link. Data is randomized,
balanced and scrambled. The 28 bits frame structure changes in the 12 bit low frequency mode, 12 bit high
frequency mode and the 10 bit mode internally and is seamless to the customer. The bidirectional control
channel data is transferred over the single serial link along with the high-speed forward data. This architecture
provides a full duplex low speed forward and backward path across the serial link together with a high speed
forward channel without the dependence on the video blanking phase.
Error Detection
The chipset provides error detection operations for validating data integrity in long distance transmission and
reception. The data error detection function offers users flexibility and usability of performing bit-by-bit data
transmission error checking. The error detection operating modes support data validation of the following signals:
•
•
Bidirectional control channel data across the serial link
Parallel video/sync data across the serial link
The chipset provides 1 parity bit on the forward channel and 4 CRC bits on the back channel for error detection
purposes. The DS90UB913/914Q chipset checks the forward and back channel serial links for errors and stores
the number of detected errors in two 8-bit registers in the Serializer and the Deserializer respectively.
To check parity errors on the forward channel, monitor registers 0x1A and 0x1B on the Deserializer. If there is a
loss of LOCK, then the counters on registers 0x1A and 0x1B are reset. Whenever there is a parity error on the
forward channel, the PASS pin will go low.
To check CRC errors on the back-channel, monitor registers 0x0A and 0x0B on the Serializer.
Description of Bidirectional Control Bus and I2C Modes
The I2C compatible interface allows programming of the DS90UB913Q, DS90UB914Q, or an external remote
device (such as image sensor) through the bidirectional control channel. Register programming transactions
to/from the DS90UB913Q/914Q chipset are employed through the clock (SCL) and data (SDA) lines. These two
signals have open drain I/Os and both lines must be pulled-up to VDDIO by an external resistor. Pull-up resistors
or current sources are required on the SCL and SDA busses to pull them high when they are not being driven
low. A logic LOW is transmitted by driving the output low. Logic HIGH is transmitted by releasing the output and
allowing it to be pulled-up externally. The appropriate pull-up resistor values will depend upon the total bus
capacitance and operating speed. The DS90UB913/914Q I2C bus data rate supports up to 400 kbps according
to I2C fast mode specifications.
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