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DS90UB913QSQ/NOPB 参数 Datasheet PDF下载

DS90UB913QSQ/NOPB图片预览
型号: DS90UB913QSQ/NOPB
PDF下载: 下载PDF文件 查看货源
内容描述: DS90UB913Q / DS90UB914Q 10-100MHz 10 / 12位DC平衡的FPD -Link的III串行器和解串与双向控制通道 [DS90UB913Q/DS90UB914Q 10-100MHz 10/12- Bit DC-Balanced FPD-Link III Serializer and Deserializer with Bidirectional Control Channel]
分类和应用: 光电二极管
文件页数/大小: 63 页 / 1331 K
品牌: TAOS [ TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS ]
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DS90UB913Q, DS90UB914Q  
www.ti.com  
SNLS420B JULY 2012REVISED APRIL 2013  
Table 4. BIST Clock Sources  
DS90UB914Q  
Reg 0x24 [2:1]  
10–bit  
Mode  
12–bit  
High Frequency Mode  
12–bit  
Low Frequency Mode  
00  
01  
10  
11  
PCLK  
100 MHz  
50 MHz  
25MHz  
PCLK  
75 MHz  
PCLK  
50 MHz  
37.5 MHz  
18.75 MHz  
25 MHz  
12.5 MHz  
Functional Description  
The DS90UB913/914Q FPD- Link III chipsets are intended to link mega-pixel camera imagers and video  
processors in ECUs. The Serializer/Deserializer chipset can operate from 10MHz to 100MHz pixel clock  
frequency. The DS90UB913Q device transforms a 10/12-bit wide parallel LVCMOS data bus along with a  
bidirectional control channel control bus into a single high-speed differential pair. The high speed serial bit stream  
contains an embedded clock and DC-balanced information which enhances signal quality to support AC  
coupling. The DS90UB914Q device receives the single serial data stream and converts it back into a 10/12-bit  
wide parallel data bus together with the control channel data bus. The DS90UB913/914Q chipsets can accept up  
to  
12 bits of DATA+2 bits SYNC for an input PCLK range of 10MHz-50MHz in the 12-bit low frequency mode  
12 bits DATA + 2 SYNC bits for an input PCLK range of 15MHz to 75MHz in the 12-bit high frequency mode  
10 bits DATA + 2 SYNC bits for an input PCLK range of 20MHz to 100MHz in the 10-bit mode.  
The DS90UB914Q chipset has a 2:1 multiplexer which allows customers to select between two Serializer inputs.  
The control channel function of the DS90UB913/DS90UB914Q chipset provides bidirectional communication  
between the image sensor and ECUs. The integrated bidirectional control channel transfers data bidirectionally  
over the same differential pair used for video data interface. This interface offers advantages over other chipsets  
by eliminating the need for additional wires for programming and control. The bidirectional control channel bus is  
controlled via an I2C port. The bidirectional control channel offers asymmetrical communication and is not  
dependent on video blanking intervals.  
The DS90UB913/914Q chipset offer customers the choice to work with different clocking schemes. The  
DS90UB913/914Q chipsets can use an external oscillator as the reference clock source for the PLL or PCLK  
from the imager as primary reference clock to the PLL.  
Transmission Media  
The DS90UB913/914Q chipset is intended to be used in a point-to-point configuration through a shielded twisted  
pair cable. The Serializer and Deserializer provide internal termination to minimize impedance discontinuities.  
The interconnect (cable and connectors) should have a differential impedance of 100 Ohms. The maximum  
length of cable that can be used is dependent on the quality of the cable (gauge, impedance), connector,  
board(discontinuities, power plane), the electrical environment (e.g power stability, ground noise, input clock  
jitter, PCLK frequency, etc). The resulting signal quality at the receiving end of the transmission media may be  
assessed by monitoring the differential eye opening of the serial data stream. A differential probe should be used  
to measure across the termination resistor at the CMLOUTP/N pins. Figure 19 illustrates the minimum eye width  
and eye height that is necessary for bit error free operation.  
DS90UB913/914Q Operation with External Oscillator as Reference Clock  
In some applications, the pixel clock that comes from the imager can have jitter which exceeds the tolerance of  
the DS90UB913/914Q chipsets. In this case, the DS90UB913Q device should be operated by using an external  
clock source as the reference clock for the DS90UB913/914Q chipsets. This is the recommended operating  
mode. The external oscillator clock output goes through a divide-by-2 circuit in the DS90UB913Q Serializer and  
this divided clock output is used as the reference clock for the imager. The output data and pixel clock from the  
imager are then fed into the DS90UB913Q device. Figure 24 shows the operation of the DS90UB13/914Q  
chipsets while using an external automotive grade oscillator.  
Copyright © 2012–2013, Texas Instruments Incorporated  
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