DS90UB913Q, DS90UB914Q
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SNLS420B –JULY 2012–REVISED APRIL 2013
Table 2. DS90UB914Q Control Registers (continued)
Addr
(Hex)
Name
Bits
Field
R/W
Default
Description
Control Channel Sequence Error Detected This
bit indicates a sequence error has been
detected in forward control channel.
1: If this bit is set, an error may have occurred
in the control channel operation
Forward Channel
Sequence Error
7
R
0
0
0: No forward channel errors have been
detected on the control channel
Clear Sequence
Error
Clears the Sequence Error Detect bit
6
5
RW
RSVD
Reserved
SDA Output Delay This field configures output
delay on the SDA output. Setting this value will
increase output delay in units of 50ns. Nominal
output delay values for SCL to SDA are:
00 : 350ns
4:3
SDA Output Delay
RW
0
01: 400ns
10: 450ns
11: 500ns
Disable Remote Writes to local registers
Setting this bit to a 1 will prevent remote writes
to local device registers from across the control
channel. This prevents writes to the
Deserializer registers from an I2C master
attached to the Serializer. Setting this bit does
not affect remote access to I2C slaves at the
Deserializer.
Speed up I2C Bus Watchdog Timer
1: Watchdog Timer expires after approximately
50µs
0x22
I2C Control 2
2
1
Local Write Disable
RW
RW
0
0
I2C Bus Timer
Speedup
0: Watchdog Timer expires after approximately
1s.
Disable I2C Bus Watchdog Timer When the I2C
Watchdog Timer may be used to detect when
the I2C bus is free or hung up following an
invalid termination of a transaction. If SDA is
high and no signaling occurs for approximately
1 second, the I2C bus will assumed to be free.
If SDA is low and no signaling occurs, the
device will attempt to clear the bus by driving 9
clocks on SCL
I2C Bus Timer
Disable
0
RW
0
General Purpose
Control
Scratch Register
0x23
0x24
0x25
7:0
7:4
GPCR
RSVD
RW
RW
0
1
Reserved
Bist Configured through Pin.
1: Bist configured through pin.
0: Bist configured through register bit
"reg_24[0]"
BIST Pin
Configuration
3
BIST Control
BIST Clock Source
See Table 4
2:1
0
BIST Clock Source
BIST Enable
RW
RW
R
00
0
BIST Control
1: Enabled
0: Disabled
Number of Forward channel Parity errors in the
BIST mode.
Parity Error Count
7:0
BIST Error Count
0
0x26–0
x3B
RESERVED
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