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DS90UB913QSQ/NOPB 参数 Datasheet PDF下载

DS90UB913QSQ/NOPB图片预览
型号: DS90UB913QSQ/NOPB
PDF下载: 下载PDF文件 查看货源
内容描述: DS90UB913Q / DS90UB914Q 10-100MHz 10 / 12位DC平衡的FPD -Link的III串行器和解串与双向控制通道 [DS90UB913Q/DS90UB914Q 10-100MHz 10/12- Bit DC-Balanced FPD-Link III Serializer and Deserializer with Bidirectional Control Channel]
分类和应用: 光电二极管
文件页数/大小: 63 页 / 1331 K
品牌: TAOS [ TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS ]
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DS90UB913Q, DS90UB914Q  
SNLS420B JULY 2012REVISED APRIL 2013  
www.ti.com  
Table 2. DS90UB914Q Control Registers (continued)  
Addr  
(Hex)  
Name  
Bits  
Field  
R/W  
Default  
Description  
Allows overriding OEN and OSS select coming  
from Pins  
1: Overrides OEN/OSS_SEL selected by pins  
0: Does NOT override OEN/OSS_SEL select  
by pins  
OEN_OSS  
Override  
7
RW  
0
6
5
OEN Select  
OSS Select  
RW  
R
0
0
OEN configuration from register  
OSS_SEL configuration from register  
Allows overriding mode select bits coming from  
back-channel  
1: Overrides MODE select bits  
0: Does not override MODE select bits  
MODE_OVERRID  
E
4
RW  
0
PIN_MODE_12–bit  
HF mode  
Status of mode select pin  
Mode and OSS  
Select  
3
2
R
R
0
0
0x1F  
PIN_MODE_10 bit  
mode  
Status of mode select pin  
Selects 12 bit high frequency mode. This bit is  
automatically updated by the mode settings  
from RX unless MODE_OVERRIDE is SET  
1: 12 bit high frequency mode is selected.  
0: 12 bit high frequency mode is not selected.  
MODE_12–bit High  
Frequency  
1
0
RW  
RW  
0
0
Selects 10 bit mode. This bit is automatically  
updated by the mode settings from RX unless  
MODE_OVERRIDE is SET  
MODE_10–bit  
mode  
1: Enables 10 bit mode.  
0: Disables 10 bit mode.  
The watchdog timer allows termination of a  
control channel transaction if it fails to complete  
within a programmed amount of time. This field  
sets the Bidirectional Control Channel  
Watchdog Timeout value in units of 2ms. This  
field should not be set to 0.  
BCC Watchdog  
timer  
7:1  
RW  
0
BCC Watchdog  
Control  
0x20  
Disable Bidirectional Control Channel  
Watchdog Timer  
1: Disables BCC Watchdog Timer operation  
0: Enables BCC Watchdog Timer operation  
BCC Watchdog  
Timer Disable  
0
RW  
RW  
RW  
RW  
0
0
0
0
I2C Pass-Through All Transactions  
0: Disabled  
1: Enabled  
I2C pass through  
all  
7
Internal SDA Hold Time This field configures  
the amount of internal hold time provided for  
the SDA input relative to the SCL input. Units  
are 50ns.  
I2C Glitch Filter Depth This field configures the  
maximum width of glitch pulses on the SCL and  
SDA inputs that will be rejected. Units are 10ns.  
0x21  
I2C Control 1  
6:4  
3:0  
I2C SDA Hold  
I2C Filter Depth  
34  
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Copyright © 2012–2013, Texas Instruments Incorporated  
Product Folder Links: DS90UB913Q DS90UB914Q  
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