DS90UB913Q, DS90UB914Q
SNLS420B –JULY 2012–REVISED APRIL 2013
www.ti.com
Table 2. DS90UB914Q Control Registers (continued)
Addr
(Hex)
Name
Bits
Field
R/W
Default
Description
7:2
RSVD
Reserved
Selects the divider for the OSC clock out on
PCLK when system is not locked and selected
by OEN/OSSSEL 0x02[5]
Oscillator output
divider select
0x3C
OSC OUT
DIVIDER SEL
1:0
RW
0
00: 50M (+/- 30%)
01: 25M (+/- 30%)
1X: 12.5M (+/- 30%)
0x3D-
0x3E
RESERVED
7:5
4
RSVD
Reserved
CML Output
Enable
0: CML Loop-through Driver is powered up
1: CML Loop-through Driver is powered down.
0x3F
CML OUT Enable
RSVD
RW
RW
1
3:0
Reserved
I2C Master SCL High Time This field configures
the high pulse width of the SCL output when
the De-Serializer is the Master on the local I2C
bus. Units are 50 ns for the nominal oscillator
clock frequency. The default value is set to
provide a minimum (4μs + 0.3μs of rise time for
cases where rise time is very fast) SCL high
time with the internal oscillator clock running at
26MHz rather than the nominal 20MHz.
0x40
SCL High Time
7:0
SCL High Time
0x82
I2C SCL Low Time This field configures the low
pulse width of the SCL output when the De-
Serializer is the Master on the local I2C bus.
This value is also used as the SDA setup time
by the I2C Slave for providing data prior to
releasing SCL during accesses over the
Bidirectional Control Channel. Units are 50 ns
for the nominal oscillator clock frequency. The
default value is set to provide a minimum
(4.7µs + 0.3µs of fall time for cases where fall
time is very fast) SCL low time with the internal
oscillator clock running at 26MHz rather than
the nominal 20MHz.
0x41
SCL Low Time
7:0
SCL Low Time
RW
0x82
7:2
1
RSVD
Reserved
1: This bit introduces multiple errors into Back
channel frame.
0: No effect
Force Back
Channel Error
RW
RW
0
0
0x42
CRC Force Error
Force One Back
Channel Error
1: This bit introduces ONLY one error into Back
channel frame. Self clearing bit
0: No effect
0
0x43-
0x4C
RESERVED
0x4D
AEQ Test Mode
Select
7
RSVD
Reserved
AEQ Bypass
Bypass AEQ and use set manual EQ value
using register 0x04
6
RW
R
0
0
5:0
7:0
RSVD
Reserved
0x4E
EQ Value
AEQ / Manual Eq
Readback
Read back the adaptive and manual
Equalization value
Table 3. Clock Sources for Forward Channel Frame on the Serializer During Normal Operation
DS90UB913Q
Reg 0x14 [2:1]
10–bit
Mode
12–bit
High Frequency Mode
12–bit
Low Frequency Mode
00
01
10
11
50 MHz
100 MHz
50 MHz
25MHz
37.5 MHz
75 MHz
25 MHz
50 MHz
25 MHz
12.5 MHz
37.5 MHz
18.75 MHz
36
Submit Documentation Feedback
Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: DS90UB913Q DS90UB914Q
TAOS [ TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS ]
