DS90UB913Q, DS90UB914Q
SNLS420B –JULY 2012–REVISED APRIL 2013
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Bidirectional Control Bus DC Timing Specifications (SCL, SDA) - I2C Compliant(1) (continued)
Over recommended supply and temperature ranges unless otherwise specified
Symbol
VIL
Parameter
Input Low Level
Conditions
SDA and SCL
Min
Typ
Max
Units
V
GND
0.3*VDDIO
VHY
VOL
IIN
Input Hysteresis
>50
mV
V
Output Low Level
Input Current
SDA, IOL=0.5mA
0
0.4
10
SDA or SCL, VIN=VDDOP OR GND
—10
µA
ns
tR
SDA Rise Time-READ
SDA Fall Time-READ
430
20
SDA, RPU = 10kΩ, Cb ≤ 400pF
(Figure 4)
tF
ns
tSU;DAT
tHD;DAT
tSP
SeeFigure 4
SeeFigure 4
560
615
50
ns
ns
ns
CIN
SDA or SCL
<5
pF
AC Timing Diagrams and Test Circuits
SDA
t
BUF
t
f
t
t
HD;STA
t
LOW
r
t
t
f
r
SCL
t
t
HD;STA
SU;STA
t
SU;STO
t
HIGH
t
t
SU;DAT
HD;DAT
STOP START
START
REPEATED
START
Figure 4. Bi-directional Control Bus Timing
Signal Pattern
Device Pin Name
T
PCLK
(RFB = H)
D
/R
IN OUT
Figure 5. “Worst Case” Test Pattern
80%
20%
80%
Vdiff
Vdiff = 0V
20%
t
t
HLT
LHT
Vdiff = (D +) - (D -)
OUT OUT
Figure 6. Serializer CML Output Load and Transition Times
100 nF
D
OUT
+
50W
50W
SCOPE
BW 8 4.0 GHz
Z
Diff
= 100W
100W
D
OUT
-
100 nF
Figure 7. Serializer CML Output Load and Transition Times
16
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