DS90UB913Q, DS90UB914Q
www.ti.com
SNLS420B –JULY 2012–REVISED APRIL 2013
Serializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
tLHT
tHLT
CML Low-to-High Transition RL = 100Ω (Figure 6)
Time
150
330
ps
CML High-to-Low Transition RL = 100Ω (Figure 6)
Time
150
330
ps
tDIS
tDIH
tPLD
tSD
Data Input Setup to PCLK
Data Input Hold from PCLK
Serializer PLL Lock Time
Serializer Delay(2)
Serializer Data Inputs
(Figure 12)
2
2
ns
ns
RL = 100Ω(1)(2), (Figure 13)
1
2
ms
RT = 100Ω
10–bit mode
Register 0x03h b[0] (TRFB = 1)
(Figure 14)
32.5T
38T
44T
ns
ns
RT = 100Ω
12–bit mode
Register 0x03h b[0] (TRFB = 1)
(Figure 14)
11.75T
13T
15T
tJIND
tJINR
tJINT
Serializer Output
Deterministic Jitter
Serializer output intrinsic deterministic
jitter . Measured (cycle-cycle) with
PRBS-7 test pattern(3)(4)
0.13
0.04
UI
UI
Serializer Output Random
Jitter
Serializer output intrinsic random jitter
(cycle-cycle). Alternating-1,0
pattern.(3)(4)
Peak-to-peak Serializer
Output Jitter
Serializer output peak-to-peak jitter
includes deterministic jitter, random
jitter, and jitter transfer from serializer
input. Measured (cycle-cycle) with
PRBS-7 test pattern.(3)(4)
0.396
UI
λSTXBW
Serializer Jitter Transfer
PCLK = 100MHz
2.2
2.2
Function -3 dB Bandwidth(5) 10–bit mode. Default Registers
PCLK = 75MHz
12–bit high frequency mode. Default
Registers
MHz
PCLK = 50MHz
2.2
12–bit low frequency mode. Default
Registers
δSTX
Serializer Jitter Transfer
Function (Peaking)(5)
PCLK = 100MHz
10–bit mode. Default Registers
1.06
1.09
PCLK = 75MHz
12–bit high frequency mode. Default
Registers
dB
PCLK = 50MHz
1.16
12–bit low frequency mode. Default
Registers
δSTXf
Serializer Jitter Transfer
Function (Peaking
Frequency)(5)
PCLK = 100MHz
10–bit mode. Default Registers
400
500
PCLK = 75MHz
12–bit high frequency mode. Default
Registers
kHz
PCLK = 50MHz
600
12–bit low frequency mode. Default
Registers
(1) tPLD and tDDLT is the time required by the serializer and deserializer to obtain lock when exiting power-down state with an active PCLK
(2) Specification is ensured by design.
(3) Typical values represent most likely parametric norms at 1.8V or 3.3V, TA = +25°C, and at the Recommended Operation Conditions at
the time of product characterization and are not specified.
(4) UI – Unit Interval is equivalent to one ideal serialized data bit width. The UI scales with PCLK frequency.
(5) Specification is ensured by characterization and is not tested in production.
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