DS90UB913Q, DS90UB914Q
SNLS420B –JULY 2012–REVISED APRIL 2013
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Deserializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
10–bit mode
Pin/Freq.
Min
10
Typ
Max
50
Units
tRCP
Receiver Output
Clock Period
PCLK (Figure 18)
12–bit high frequency mode
12–bit low frequency mode
10–bit mode
13.33
10
66.66
100
55
ns
tPDC
PCLK Duty Cycle
PCLK
PCLK
45
50
50
50
12–bit high frequency mode
12–bit low frequency mode
VDDIO: 1.71V to 1.89V or 3.0V
40
60
%
40
60
LVCMOS Low-to-
High Transition Time to 3.6V,
tCLH
tCHL
1.3
1.3
1
2
2.8
2.8
4
CL = 8 pF (lumped load)
ns
LVCMOS High-to-
Low Transition Time
Default Registers
2
(Figure 16)(1)
LVCMOS Low-to-
High Transition Time to 3.6V,
VDDIO: 1.71V to 1.89V or 3.0V
ROUT[11:0], HS, VS
ROUT[11:0], HS, VS
tCLH
tCHL
2.5
2.5
CL = 8 pF (lumped load)
ns
ns
LVCMOS High-to-
Low Transition Time
Default Registers
1
4
(Figure 16)(1)
ROUT Setup Data to VDDIO: 1.71V to 1.89V or 3.0V
PCLK
tROS
tROH
0.38T
0.5T
0.5T
to 3.6V,
CL = 8 pF (lumped load)
Default Registers (Figure 18)
ROUT Hold Data to
PCLK
0.38T
154T
109T
10–bit mode
158T
112T
Default Registers
12–bit low frequency
tDD
Deserializer Delay
Register 0x03h b[0] (RRFB = 1) mode
ns
(Figure 17)(1)
12–bit high frequency
73T
75T
22
mode
With Adaptive Equalization
(Figure 15)
10–bit mode
15
15
12–bit low frequency
mode
Deserializer Data
Lock Time
22
tDDLT
ms
12–bit high frequency
mode
15
20
22
30
tRCJ
Receiver Clock Jitter PCLK
SSCG[3:0] = OFF(1)
10–bit mode
PCLK=100MHz
12–bit low frequency
mode
PCLK=50MHz
22
35
ps
12–bit high frequency
mode
45
90
PCLK=75MHz
tDPJ
Deserializer Period
Jitter
PCLK
SSCG[3:0] = OFF(2)(1)
10–bit mode
PCLK=100MHz
170
180
815
330
12–bit low frequency
mode
ps
PCLK=50MHz
12–bit high frequency
mode
300
515
PCLK=75MHz
(1) Specification is ensured by characterization and is not tested in production.
(2) tDPJ is the maximum amount the period is allowed to deviate measured over 30,000 samples.
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