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DS90UB913QSQ/NOPB 参数 Datasheet PDF下载

DS90UB913QSQ/NOPB图片预览
型号: DS90UB913QSQ/NOPB
PDF下载: 下载PDF文件 查看货源
内容描述: DS90UB913Q / DS90UB914Q 10-100MHz 10 / 12位DC平衡的FPD -Link的III串行器和解串与双向控制通道 [DS90UB913Q/DS90UB914Q 10-100MHz 10/12- Bit DC-Balanced FPD-Link III Serializer and Deserializer with Bidirectional Control Channel]
分类和应用: 光电二极管
文件页数/大小: 63 页 / 1331 K
品牌: TAOS [ TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS ]
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DS90UB913Q, DS90UB914Q  
SNLS420B JULY 2012REVISED APRIL 2013  
www.ti.com  
Units  
Electrical Characteristics(1)(2)(3) (continued)  
Over recommended operating supply and temperature ranges unless otherwise specified.  
Symbol  
Parameter  
Conditions  
Min  
Typ  
Max  
IDDR  
Deserializer (Rx) VDDn VDDn=1.89V  
f=100MHz,  
10–bit mode  
64  
110  
Supply Current  
CL=4pF  
(includes load current) Worst Case Pattern  
f=75MHz,  
12–bit high freq  
mode  
67  
114  
96  
f=50MHz,  
12–bit low freq  
mode  
63  
57  
60  
mA  
VDDn=1.89V  
CL=4pF  
f=100MHz,  
10–bit mode  
Random Pattern  
f=75MHz,  
12–bit high freq  
mode  
f=50MHz,  
12–bit low freq  
mode  
56  
42  
42  
IDDRZ  
Deserializer (Rx)  
PBB=0V  
VDDIO=1.89V  
Default Registers  
Supply Current Power- All other LVCMOS  
400  
400  
down  
Inputs=0V  
µA  
µA  
PBB=0V  
All other LVCMOS  
Inputs=0V  
VDDIO=3.6V  
Default Registers  
IDDIORZ  
Deserializer (Rx) VDD PDB = 0V  
Supply Current Power- All other LVCMOS  
VDDIO = 1.89V  
VDDIO = 3.6V  
8
40  
360  
800  
down  
Inputs = 0V  
Recommended Serializer Timing for PCLK(1)  
Over recommended operating supply and temperature ranges unless otherwise specified.  
Symbol  
tTCP  
Parameter  
Conditions  
10–bit Mode  
Pin/Freq  
Min  
10  
Typ  
T
Max  
50  
Units  
ns  
Transmit Clock Period  
12–bit high frequency mode  
12–bit low frequency mode  
13.33  
20  
T
66.66  
100  
ns  
T
ns  
tTCIH  
tTCIL  
tCLKT  
Transmit Clock Input High  
Time  
0.4T  
0.5T  
0.6T  
ns  
Transmit Clock Input Low  
Time  
0.4T  
0.5T  
0.5T  
0.5T  
2.5T  
2.5T  
0.6T  
0.3T  
0.3T  
ns  
ns  
ns  
PCLK Input Transition  
Time  
(Figure 11)  
20MHz–100 MHz, 10 bit mode  
15MHz -75MHz, 12 bit high  
frequency mode  
10MHz-50MHz, 12 bit low  
frequency mode  
0.5T  
2.5T  
0.1T  
0.3T  
ns  
ns  
tJIT0  
tJIT1  
tJIT2  
PCLK Input Jitter (PCLK  
from imager mode)  
Refer to  
Jitter freq>f/40  
f=10–100M  
Hz  
PCLK Input Jitter  
(External Oscillator mode) Jitter freq>f/40  
Refer to  
f=10–100M  
Hz  
1T  
ns  
UI  
External Oscillator Jitter  
0.1  
(1) Recommended Input Timing Requirements are input specifications and not tested in production.  
12  
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Product Folder Links: DS90UB913Q DS90UB914Q