DS90UB913Q, DS90UB914Q
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SNLS420B –JULY 2012–REVISED APRIL 2013
Deserializer Switching Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Pin/Freq.
Min
Typ
Max
Units
tDCCJ
Deserializer Cycle-
PCLK
10–bit mode
PCLK=100MHz
440
1760
to-Cycle Clock Jitter SSCG[3:0] = OFF(3)(1)
12–bit low frequency
mode
PCLK=50MHz
460
565
730
985
ps
12–bit high frequency
mode
PCLK=75MHz
fdev
Spread Spectrum
Clocking Deviation
Frequency
LVCMOS Output Bus
10 MHz–100 MHz
±0.5 to
±1.5
SSC[3:0] = ON (Figure 23)(1)
%
fmod
Spread Spectrum
Clocking Modulation
Frequency
10 MHz–100 MHz
5 to 50
kHz
(3) tDCCJ is the maximum amount of jitter between adjacent clock cycles measured over 30,000 samples.
AC Timing Specifications (SCL, SDA) - I2C Compliant
Over recommended supply and temperature ranges unless otherwise specified.(Figure 4)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Recommended Input Timing Requirements
Standard Mode
>0
>0
100
400
kHz
kHz
µs
µs
µs
µs
µs
µs
µs
µs
µs
ns
ns
ns
µs
µs
µs
µs
ns
ns
ns
ns
fSCL
SCL Clock Frequency
SCL Low Period
Fast Mode
Standard Mode
Fast Mode
4.7
1.3
4.0
0.6
4.0
0.6
4.7
0.6
0
tLOW
tHIGH
tHD:STA
tSU:STA
tHD:DAT
tSU:DAT
tSU:STO
tBUF
Standard Mode
Fast Mode
SCL High Period
Standard Mode
Fast Mode
Hold time for a start or a repeated start
condition
Standard Mode
Fast Mode
Set Up time for a start or a repeated
start condition
Standard Mode
Fast Mode
3.45
900
Data Hold Time
0
Standard Mode
Fast Mode
250
100
4.0
0.6
4.7
1.3
Data Set Up Time
Standard Mode
Fast Mode
Set Up Time for STOP Condition
Bus Free time between Stop and Start
SCL & SDA Rise Time
SCL & SDA Fall Time
Standard Mode
Fast Mode
Standard Mode
Fast Mode
1000
300
300
300
tr
Standard Mode
Fast Mode
tf
Bidirectional Control Bus DC Timing Specifications (SCL, SDA) - I2C Compliant(1)
Over recommended supply and temperature ranges unless otherwise specified
Symbol
Recommended Input Timing Requirements
VIH Input High Level
Parameter
Conditions
Min
Typ
Max
Units
SDA and SCL
0.7*VDDIO
VDDIO
V
(1) Specification is ensured by design.
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