CC2430
Peripherals
: DMA Controller
DMAREQ (0xD7) – DMA Channel Start Request and Status
Bit
7:5
4
Name
-
Reset
000
0
R/W
Description
R0
Not used
DMAREQ4
R/W1
H0
DMA transfer request, channel 4
When set to 1 activate the DMA channel (has the same
effect as a single trigger event.). Only by setting the armed
bit to 0 in the DMAARMregister, can the channel be
stopped if already started.
This bit is cleared when the DMA channel is granted
access.
3
2
1
0
DMAREQ3
DMAREQ2
DMAREQ1
DMAREQ0
0
0
0
0
R/W1
H0
DMA transfer request, channel 3
When set to 1 activate the DMA channel (has the same
effect as a single trigger event.). Only by setting the armed
bit to 0 in the DMAARMregister, can the channel be
stopped if already started.
This bit is cleared when the DMA channel is granted
access.
R/W1
H0
DMA transfer request, channel 2
When set to 1 activate the DMA channel (has the same
effect as a single trigger event.). Only by setting the armed
bit to 0 in the DMAARMregister, can the channel be
stopped if already started.
This bit is cleared when the DMA channel is granted
access.
R/W1
H0
DMA transfer request, channel 1
When set to 1 activate the DMA channel (has the same
effect as a single trigger event.). Only by setting the armed
bit to 0 in the DMAARMregister, can the channel be
stopped if already started.
This bit is cleared when the DMA channel is granted
access.
R/W1
H0
DMA transfer request, channel 0
When set to 1 activate the DMA channel (has the same
effect as a single trigger event.). Only by setting the armed
bit to 0 in the DMAARMregister, can the channel be
stopped if already started.
This bit is cleared when the DMA channel is granted
access.
DMA0CFGH (0xD5) – DMA Channel 0 Configuration Address High Byte
Bit
Name
Reset
R/W
Description
7:0
DMA0CFG[15:8]
0x00
R/W
The DMA channel 0 configuration address, high order
DMA0CFGL (0xD4) – DMA Channel 0 Configuration Address Low Byte
Bit
Name
Reset
R/W
Description
7:0
DMA0CFG[7:0]
0x00
R/W
The DMA channel 0 configuration address, low order
DMA1CFGH (0xD3) – DMA Channel 1-4 Configuration Address High Byte
Bit
Name
Reset
R/W
Description
7:0
DMA1CFG[15:8]
0x00
R/W
The DMA channel 1-4 configuration address, high order
CC2430 Data Sheet (rev. 2.1) SWRS036F
Page 97 of 211
TAOS [ TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS ]
