CC2430
Peripherals : 16-bit timer, Timer1
13.6 16-bit timer, Timer1
Timer 1 is an independent 16-bit timer which
supports typical timer/counter functions such
as input capture, output compare and PWM
functions. The timer has three independent
capture/compare channels. The timer uses
one I/O pin per channel. The timer is used for
a wide range of control and measurement
applications and the availability of up/down
count mode with three channels will for
example allow implementation of motor control
applications.
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Three capture/compare channels
Rising, falling or any edge input capture
Set, clear or toggle output compare
Free-running, modulo or up/down counter
operation
Clock prescaler for divide by 1, 8, 32 or
128
Interrupt request generated on each
capture/compare and terminal count
DMA trigger function
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The features of Timer 1 are as follows:
13.6.1
16-bit Timer Counter
The timer consists of a 16-bit counter that
increments or decrements at each active clock
edge. The period of the active clock edges is
defined by the register bits CLKCON.TICKSPD
which sets the global division of the system
clock giving a variable clock tick frequency
from 0.25 MHz to 32 MHz (given the use of the
32 MHz XOSC as clock source). This is further
divided in Timer 1 by the prescaler value set
by T1CTL.DIV. This prescaler value can be
from 1, 8, 32, or 128. Thus the lowest clock
frequency used by Timer 1 is 1953.125 Hz and
the highest is 32 MHz when the 32 MHz
crystal oscillator is used as system clock
source. When the 16 MHz RC oscillator is
used as system clock source then the highest
clock frequency used by Timer 1 is 16 MHz.
It is possible to read the 16-bit counter value
through the two 8-bit SFRs; T1CNTH and
T1CNTL, containing the high-order byte and
low-order byte respectively. When the T1CNTL
is read, the high-order byte of the counter at
that instant is buffered in T1CNTH so that the
high-order byte can be read from T1CNTH.
Thus T1CNTLshall always be read first before
reading T1CNTH.
All write accesses to the T1CNTL register will
reset the 16-bit counter.
The counter produces an interrupt request
when the terminal count value (overflow) is
reached. It is possible to start and halt the
counter with T1CTL control register settings.
The counter is started when a value other than
00 is written to T1CTL.MODE. If 00 is written to
T1CTL.MODE the counter halts at its present
value.
The counter operates as either a free-running
counter, a modulo counter or as an up/down
counter for use in centre-aligned PWM.
13.6.2
Timer 1 Operation
In general, the control register T1CTL is used
to control the timer operation. The various
modes of operation are described below.
13.6.3
Free-running Mode
In the free-running mode of operation the
counter starts from 0x0000 and increments at
each active clock edge. When the counter
reaches 0xFFFF (overflow) the counter is
reached, both the IRCON.T1IF and the
T1CTL.OVFIF flag are set. An interrupt
request is generated if the corresponding
interrupt mask bit TIMIF.OVFIM is set
together with IEN1.T1EN. The free-running
mode can be used to generate independent
time intervals and output signal frequencies.
loaded
with
0x0000
and
continues
incrementing its value as shown in Figure 20.
When the terminal count value 0xFFFF is
CC2430 Data Sheet (rev. 2.1) SWRS036F
Page 99 of 211
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