CC2430
Peripherals : DMA Controller
Byte
Bit
Name
Description
Offset
Mode of 8th bit for VLEN transfer length; only applicable when WORDSIZE=0.
M8
7
2
0 : Use all 8 bits for transfer count
1 : Use 7 LSB for transfer count
PRIORITY[1:0]
7
1:0
The DMA channel priority:
00 : Low, CPU has priority.
01 : Guaranteed, DMA at least every second try.
10 : High, DMA has priority
11 : Highest, DMA has priority. Reserved for DMA port access.
13.5.8
DMA registers
This section describes the SFR registers associated with the DMA Controller
DMAARM (0xD6) – DMA Channel Arm
Bit
Name
Reset
R/W
Description
7
ABORT
0
R0/W
DMA abort. This bit is used to stop ongoing DMA transfers.
Writing a 1 to this bit will abort all channels which are selected
by setting the corresponding DMAARM bit to 1
0 : Normal operation
1 : Abort all selected channels
6:5
4
-
00
0
R/W
Not used
DMAARM4
R/W1
DMA arm channel 4
This bit must be set in order for any DMA transfers to occur on
the channel. For non-repetitive transfer modes, the bit is
automatically cleared upon completion.
3
2
1
0
DMAARM3
DMAARM2
DMAARM1
DMAARM0
0
0
0
0
R/W1
R/W1
R/W1
R/W1
DMA arm channel 3
This bit must be set in order for any DMA transfers to occur on
the channel. For non-repetitive transfer modes, the bit is
automatically cleared upon completion.
DMA arm channel 2
This bit must be set in order for any DMA transfers to occur on
the channel. For non-repetitive transfer modes, the bit is
automatically cleared upon completion.
DMA arm channel 1
This bit must be set in order for any DMA transfers to occur on
the channel. For non-repetitive transfer modes, the bit is
automatically cleared upon completion.
DMA arm channel 0
This bit must be set in order for any DMA transfers to occur on
the channel. For non-repetitive transfer modes, the bit is
automatically cleared upon completion.
CC2430 Data Sheet (rev. 2.1) SWRS036F
Page 96 of 211
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