CC2430
Peripherals : DMA Controller
Table 42: DMA Configuration Data Structure
Byte
Bit
Name
Description
Offset
SRCADDR[15:8]
SRCADDR[7:0]
DESTADDR[15:8]
0
1
2
7:0
7:0
7:0
The DMA channel source address, high
The DMA channel source address, low
The DMA channel destination address, high. Note that flash memory is not directly
writeable.
DESTADDR[7:0]
VLEN[2:0]
3
4
7:0
7:5
The DMA channel destination address, low. Note that flash memory is not directly
writeable.
Variable length transfer mode. In word mode, bits 12:0 of the first word is considered
as the transfer length.
000
001
Use LEN for transfer count
Transfer the number of bytes/words specified by first byte/word + 1 (up
to a maximum specified by LEN). Thus transfer count excludes length
byte/word
010
Transfer the number of bytes/words specified by first byte/word (up to a
maximum specified by LEN). Thus transfer count includes length
byte/word.
011
100
Transfer the number of bytes/words specified by first byte/word + 2 (up
to a maximum specified by LEN).
Transfer the number of bytes/words specified by first byte/word + 3 (up
to a maximum specified by LEN).
101
110
111
reserved
reserved
Alternative for using LEN as transfer count
LEN[12:8]
LEN[7:0]
4
5
4:0
7:0
The DMA channel transfer count.
Used as maximum allowable length when VLEN = 000/111. The DMA channel
counts in words when in WORDSIZE mode, and in bytes otherwise.
The DMA channel transfer count.
Used as maximum allowable length when VLEN = 000/111. The DMA channel
counts in words when in WORDSIZE mode, and in bytes otherwise.
WORDSIZE
6
6
7
Selects whether each DMA transfer shall be 8-bit (0) or 16-bit (1).
TMODE[1:0]
6:5
The DMA channel transfer mode:
00 : Single
01 : Block
10 : Repeated single
11 : Repeated block
TRIG[4:0]
6
7
4:0
7:6
Select DMA trigger to use
00000 : No trigger (writing to DMAREQis only trigger)
00001 : The previous DMA channel finished
00010 – 11110 : Selects one of the triggers shown in Table 41, in that order.
SRCINC[1:0]
Source address increment mode (after each transfer):
00 : 0 bytes/words
01 : 1 bytes/words
10 : 2 bytes/words
11 : -1 bytes/words
DESTINC[1:0]
IRQMASK
7
7
5:4
Destination address increment mode (after each transfer):
00 : 0 bytes/words
01 : 1 bytes/words
10 : 2 bytes/words
11 : -1 bytes/words
3
Interrupt Mask for this channel.
0 : Disable interrupt generation
1 : Enable interrupt generation upon DMA channel done
CC2430 Data Sheet (rev. 2.1) SWRS036F
Page 95 of 211
TAOS [ TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS ]
