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CC2430F32RTC 参数 Datasheet PDF下载

CC2430F32RTC图片预览
型号: CC2430F32RTC
PDF下载: 下载PDF文件 查看货源
内容描述: 真正的系统级芯片解决方案的2.4 GHz IEEE 802.15.4 / ZigBee的 [A True System-on-Chip solution for 2.4 GHz IEEE 802.15.4 / ZigBee]
分类和应用: 电信集成电路
文件页数/大小: 212 页 / 1862 K
品牌: TAOS [ TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS ]
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CC2430  
Peripherals  
: DMA Controller  
Table 41: DMA Trigger Sources  
DMA  
Trigger  
number  
DMA Trigger  
name  
Functional unit  
Description  
DMA  
0
NONE  
No trigger, setting DMAREQ.DMAREQx bit starts transfer  
DMA channel is triggered by completion of previous channel  
Timer 1, compare, channel 0  
Timer 1, compare, channel 1  
Timer 1, compare, channel 2  
Timer 2, compare  
DMA  
1
PREV  
Timer 1  
Timer 1  
Timer 1  
Timer 2  
Timer 2  
Timer 3  
Timer 3  
Timer 4  
Timer 4  
Sleep Timer  
IO Controller  
IO Controller  
USART0  
2
T1_CH0  
T1_CH1  
T1_CH2  
T2_COMP  
T2_OVFL  
T3_CH0  
T3_CH1  
T4_CH0  
T4_CH1  
ST  
3
4
5
6
Timer 2, overflow  
7
Timer 3, compare, channel 0  
Timer 3, compare, channel 1  
Timer 4, compare, channel 0  
Timer 4, compare, channel 1  
Sleep Timer compare  
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
IOC_0  
Port 0 I/O pin input transition9  
Port 1 I/O pin input transition9  
USART0 RX complete  
IOC_1  
URX0  
USART0  
UTX0  
USART0 TX complete  
USART1  
URX1  
USART1 RX complete  
USART1  
UTX1  
USART1 TX complete  
Flash  
FLASH  
Flash data write complete  
controller  
Radio  
ADC  
ADC  
ADC  
ADC  
ADC  
ADC  
ADC  
ADC  
ADC  
AES  
AES  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
RADIO  
RF packet byte received/transmit  
ADC_CHALL  
ADC_CH11  
ADC_CH21  
ADC_CH32  
ADC_CH42  
ADC_CH53  
ADC_CH63  
ADC_CH74  
ADC_CH84  
ENC_DW  
ADC end of a conversion in a sequence, sample ready  
ADC end of conversion channel 0 in sequence, sample ready  
ADC end of conversion channel 1 in sequence, sample ready  
ADC end of conversion channel 2 in sequence, sample ready  
ADC end of conversion channel 3 in sequence, sample ready  
ADC end of conversion channel 4 in sequence, sample ready  
ADC end of conversion channel 5 in sequence, sample ready  
ADC end of conversion channel 6 in sequence, sample ready  
ADC end of conversion channel 7 in sequence, sample ready  
AES encryption processor requests download input data  
AES encryption processor requests upload output data  
ENC_UP  
9
Using this trigger source must be aligned with port interrupt enable bits, PICTL.P0IENL/H and  
P1IEN.Note that all interrupt enabled port pins will generate a trigger and the trigger is generated on  
each level change on the enabled input (0-1 gives a trigger as does 1-0).  
CC2430 Data Sheet (rev. 2.1) SWRS036F  
Page 94 of 211  
 
 
 
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