CC2430
Peripherals
bytes/words
:
DMA Controller
Figure 19 shows the VLEN options.
4. Transfer
number
of
commanded by first byte/word
+
3
(transfers the length byte/word, and then
as many bytes/words as dictated by length
byte/word + 2)
byte/word n+2
byte/word n+1
byte/word n
byte/word n+1
byte/word n
byte/word n
byte/word n-1
byte/word n-1
byte/word n-1
byte/word n-1
byte/word 3
byte/word 2
byte/word 1
LENGTH=n
byte/word 3
byte/word 2
byte/word 1
LENGTH=n
byte/word 3
byte/word 2
byte/word 1
LENGTH=n
byte/word 3
byte/word 2
byte/word 1
LENGTH=n
VLEN=001
VLEN=010
VLEN=011
VLEN=100
Figure 19: Variable Length (VLEN) Transfer Options
Trigger Event
13.5.2.5
Each DMA channel can be set up to sense on
a single trigger. This field determines which
trigger the DMA channel shall sense.
13.5.2.6
Source and Destination Increment
When the DMA channel is armed or rearmed
the source and destination addresses are
transferred to internal address pointers. The
possibilities for address increment are :
• Increment by two. The address pointer
shall increment two counts after each
transfer.
• Decrement by one. The address pointer
shall decrement one count after each
transfer.
• Increment by zero. The address pointer
shall remain fixed after each transfer.
• Increment by one. The address pointer
shall increment one count after each
transfer.
13.5.2.7
DMA Transfer Mode
The transfer mode determines how the DMA
channel behaves when it starts transferring
data. There are four transfer modes described
below:
the CPU is notified and the DMA channel is
disarmed.
Repeated single: On a trigger a single DMA
transfer occurs and the DMA channel awaits
the next trigger. After the number of transfers
specified by the transfer count are completed,
the CPU is notified and the DMA channel is
rearmed.
Single: On a trigger a single DMA transfer
occurs and the DMA channel awaits the next
trigger. After the number of transfers specified
by the transfer count, are completed, the CPU
is notified and the DMA channel is disarmed.
Repeated block: On a trigger the number of
DMA transfers specified by the transfer count
is performed as quickly as possible, after
which the CPU is notified and the DMA
channel is rearmed.
Block: On a trigger the number of DMA
transfers specified by the transfer count is
performed as quickly as possible, after which
CC2430 Data Sheet (rev. 2.1) SWRS036F
Page 91 of 211
TAOS [ TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS ]
