CC2430
Peripherals : DMA Controller
read from the source address. The user must
ensure that the destination is writable.
Source and Destination Increment: The
source and destination addresses can be
controlled to increment or decrement or not
change.
Transfer count: The number of transfers to
perform before rearming or disarming the DMA
channel and alerting the CPU with an interrupt
request. The length can be defined in the
configuration or it can be defined as described
next as VLEN setting.
Transfer
mode:
The
transfer
mode
determines whether the transfer should be a
single transfer or a block transfer, or repeated
versions of these.
VLEN setting: The DMA channel is capable of
variable length transfers using the first byte or
word to set the transfer length. When doing
this, various options regarding how to count
number of bytes to transfer are available.
Byte or word transfers: Determines whether
each DMA transfer should be 8-bit (byte) or
16-bit (word).
Interrupt Mask: An interrupt request is
generated upon completion of the DMA
transfer. The interrupt mask bit controls if the
interrupt generation is enabled or disabled.
Priority: The priority of the DMA transfers for
the DMA channel in respect to the CPU and
other DMA channels and access ports.
M8: Decide whether to use seven or eight bits
of length byte for transfer length. This is only
applicable when doing byte transfers.
Trigger event: All DMA transfers are initiated
by so-called DMA trigger events. This trigger
either starts a DMA block transfer or a single
DMA transfer. In addition to the configured
trigger, a DMA channel can always be
A detailed description of all configuration
parameters are given in the sections 13.5.2.1
to 13.5.2.11.
triggered
by
setting
its
designated
DMAREQ.DMAREQx flag. The DMA trigger
sources are described in Table 41 on page 94.
13.5.2.1
Source Address
The address in XDATA memory where the
DMA channel shall start to read data.
13.5.2.2
Destination Address
The first address to which the DMA channel
should write the data read from the source
address. The user must ensure that the
destination is writable.
13.5.2.3
Transfer Count
The number of bytes/words needed to be
transferred for the DMA transfer to be
complete. When the transfer count is reached,
the DMA controller rearms or disarms the DMA
channel and alerts the CPU with an interrupt
request. The transfer count can be defined in
the configuration or it can be defined as a
variable length described in the next section.
13.5.2.4
VLEN Setting
The DMA channel is capable of using the first
byte or word (for word, bits 12:0 are used) in
source data as the transfer length. This allows
variable length transfers. When using variable
length transfer, various options regarding how
to count number of bytes to transfer is given.
In any case, the transfer count (LEN) setting is
used as maximum transfer count. If the
transfer length specified by the first byte or
word is greater than LEN, then LEN
bytes/words will be transferred. When using
variable length transfers, then LEN should be
set to the largest allowed transfer length plus
one.
Options which can be set with VLEN are the
following:
1. Transfer
number
of
bytes/words
commanded by first byte/word
+
1
(transfers the length byte/word, and then
as many bytes/words as dictated by length
byte/word)
2. Transfer
number
of
bytes/words
commanded by first byte/word
3. Transfer number of
bytes/words
commanded by first byte/word
+
2
(transfers the length byte/word, and then
as many bytes/words as dictated by length
byte/word + 1)
Note that the M8 bit (see page 92) is only used
when byte size transfers are chosen.
CC2430 Data Sheet (rev. 2.1) SWRS036F
Page 90 of 211
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