SM59A16U1
8-Bit Micro-controller
64KB with ISP Flash
& 6K+256B RAM embedded
from SPITXD, this bit will be cleared automatically.
SPIRXIF: Receive Interrupt Flag.
This bit is set after the SPIRXD is loaded with a newly receive data.
SPIRDR: Receive Data Ready.
The MCU must clear this bit after it gets the data from SPIRXD register. The SPI
module is able to write new data into SPIRXD only when this bit is cleared.
SPIRS: Receive Start.
This bit set to “1” to inform the SPI module to receive the data into SPIRXD register.
15.4
SPI Transmit Data Buffer (SPITXD )
Mnemonic: SPITXD
Address: F3H
7
6
5
4
3
2
1
0
Reset
00H
SPITXD[7:0]
SPITXD[7:0]: SPI Receive Data Buffer
15.5
SPI Receive Data Buffer (SPIRXD)
Mnemonic: SPIRXD
Address: F4H
7
6
5
4
3
2
1
0
Reset
00H
SPIRXD[7:0]
SPIRXD[7:0]: Receive data buffer.
P.S. MISO pin must be float when SS or CS no-active in slave mode.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M071 Ver A SM59A16U1 04/12/2013
- 107 -
SYNCMOS [ SYNCMOS TECHNOLOGIES,INC ]
