UPSD3212C, UPSD3212CV
PSD MODULE REGISTER DESCRIPTION AND ADDRESS OFFSET
Table 61 shows the offset addresses to the PSD
MODULE registers relative to the CSIOP base ad-
dress. The CSIOP space is the 256 bytes of ad-
dress that is allocated by the user to the internal
PSD MODULE registers. Table 61 provides brief
descriptions of the registers in CSIOP space. The
following section gives a more detailed descrip-
tion.
Table 61. Register Address Offset
1
Register Name
Data In
Port A Port B Port C Port D
Description
Other
00
02
01
03
10
11
Reads Port pin as input, MCU I/O Input Mode
Selects mode between MCU I/O or Address Out
Control
Stores data for output to Port pins, MCU I/O
Output Mode
Data Out
Direction
04
06
05
07
12
14
13
15
Configures Port pin as input or output
Configures Port pins as either CMOS or Open
Drain on some pins, while selecting high slew rate
on other pins.
Drive Select
08
09
16
17
Input Macrocell
Enable Out
0A
0C
0B
0D
18
1A
Reads Input Macrocells
Reads the status of the output enable to the I/O
Port driver
1B
Output Macrocells
AB
READ – reads output of macrocells AB
WRITE – loads macrocell flip-flops
20
20
21
Output Macrocells
BC
READ – reads output of macrocells BC
WRITE – loads macrocell flip-flops
21
23
Mask Macrocells AB 22
Mask Macrocells BC
22
23
Blocks writing to the Output Macrocells AB
Blocks writing to the Output Macrocells BC
Primary Flash
Protection
C0
C2
Read-only – Primary Flash Sector Protection
Secondary Flash
memory Protection
Read-only – PSD MODULE Security and
Secondary Flash memory Sector Protection
PMMR0
PMMR2
Page
B0
B4
E0
Power Management Register 0
Power Management Register 2
Page Register
Places PSD MODULE memory areas in Program
and/or Data space on an individual basis.
VM
E2
Note: 1. Other registers that are not part of the I/O ports.
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STMICROELECTRONICS [ ST ]
