UPSD3212C, UPSD3212CV
Address Register (S2ADR)
This 8-bit register may be loaded with the 7-bit
slave address to which the controller will respond
when programmed as a slave receive/transmitter.
2
the I C unit to specify the start/stop detection time
to work with the large range of MCU frequency val-
ues supported. For example, with a system clock
of 40MHz.
The Start/Stop Hold Time Detection and System
Clock registers (Tables 57 and 58) are included in
Table 56. Address Register (S2ADR)
7
6
5
4
3
2
1
0
SLA6
SLA5
SLA4
SLA3
SLA2
SLA1
SLA0
—
Note: SLA6 to SLA0: Own slave address.
Table 57. Start /Stop Hold Time Detection Register (S2SETUP)
Address Register Name Reset Value
Note
To control the start/stop hold time detection for the multi-master
I²C module in Slave Mode
SFR
D2h
S2SETUP
00h
Table 58. System Cock of 40MHz
Number of Sample
Clock (f /2 – >
S1SETUP,
S2SETUP Register
Value
Required Start/
Stop Hold Time
Note
OSC
50ns)
When Bit 7 (enable bit) = 0, the number of
sample clock is 1EA (ignore Bit 6 to Bit 0)
00h
1EA
50ns
80h
81h
82h
...
1EA
2EA
3EA
...
50ns
100ns
150ns
...
8Bh
...
12EA
...
600ns
...
Fast Mode I²C Start/Stop hold time specification
FFh
128EA
6000ns
Table 59. System Clock Setup Examples
S1SETUP,
S2SETUP Register
Number of Sample
System Clock
40MHz (f /2 – > 50ns)
Required Start/Stop Hold Time
Clock
Value
8Bh
89h
12 EA
9 EA
6 EA
3 EA
600ns
600ns
600ns
750ns
OSC
30MHz (f
/2 – > 66.6ns)
OSC
20MHz (f
8MHz (f
/2 – > 100ns)
86h
OSC
/2 – > 250ns)
83h
OSC
78/152
STMICROELECTRONICS [ ST ]
