UPSD3212C, UPSD3212CV
Table 49. PWM SFR Memory Map
Bit Register Name
SFR
Reset
Value
Reg Name
Addr
Comments
7
6
5
4
3
2
1
0
PWM
Control
Polarity
A1
A2
A3
A4
PWMCON PWML PWMP PWME CFG4
CFG3 CFG2 CFG1
CFG0
00
00
00
00
PWM0
Output
Duty Cycle
PWM0
PWM1
PWM2
PWM1
Output
Duty Cycle
PWM2
Output
Duty Cycle
PWM3
Output
Duty Cycle
A5
AA
AB
PWM3
PWM4P
PWM4W
00
00
00
PWM 4
Period
PWM 4
Pulse
Width
Prescaler 0
Low (8-bit)
B1
B2
B3
B4
PSCL0L
PSCL0H
PSCL1L
PSCL1H
00
00
00
00
Prescaler 0
High (8-bit)
Prescaler 1
Low (8-bit)
Prescaler 1
High (8-bit)
PWMCON Register Bit Definition:
– PWML = PWM 0-3 polarity control
– PWMP = PWM 4 polarity control
– PWME = PWM enable (0 = disabled, 1= enabled)
– CFG3..CFG0 = PWM 0-3 Output (0 = Open Drain; 1 = Push-Pull)
– CFG4 = PWM 4 Output (0 = Open Drain; 1 = Push-Pull)
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STMICROELECTRONICS [ ST ]
