UPSD3212C, UPSD3212CV
Table 46. ADC SFR Memory Map
Bit Register Name
SFR
Addr Name
Reg
Reset
Comments
Value
7
6
5
4
3
2
1
0
8-bit
00 Prescaler for
ADC clock
95
ASCL
ADC Data
00
96
97
ADAT
ADAT7
ADAT6 ADAT5 ADAT4 ADAT3 ADAT2 ADAT1 ADAT0
Register
ADC Control
ACON
ADEN
ADS1
ADS0
ADST
ADSF
00
Register
Table 47. Description of the ACON Bits
Bit
Symbol
—
Function
7 to 6
Reserved
ADEN
ADC Enable Bit: 0 : ADC shut off and consumes no operating current
5
4
1 : enable ADC
Reserved
—
ADS1, ADS0 Analog channel select
0, 0
0, 1
Channel0 (ACH0)
3 to 2
Channel1 (ACH1)
1, 0
Channel2 (ACH2)
1, 1
Channel3 (ACH3)
ADST
ADC Start Bit:
0 : force to zero
1
0
1 : start an ADC; after one cycle, bit is cleared to '0'
ADSF
ADC Status Bit: 0 : A/D conversion is in process
1 : A/D conversion is completed, not in process
Table 48. ADC Clock Input
MCU Clock Frequency
Prescaler Register Value
ADC Clock
6.7MHz
40MHz
36MHz
24MHz
12MHz
2
2
1
0
6MHz
6MHz
6MHz
69/152
STMICROELECTRONICS [ ST ]
