UPSD3212C, UPSD3212CV
Figure 33. Serial Port Mode 3, Block Diagram
Timer1
Overflow
Timer2
Overflow
Internal Bus
TB8
S
Write
to
SBUF
D
TxD
Q
SBUF
÷2
CL
0
1
Zero Detector
SMOD
0
0
1
Shift
Data
Start
TCLK
Tx Control
TI
Send
÷16
Tx Clock
Serial
1
Port
Interrupt
RCLK
÷16
Sample
1-to-0
Transition
Detector
Load SBUF
Shift
RI
Rx Clock
Start
Rx Control
1FFh
Rx Detector
Input Shift Register
Load
SBUF
RxD
Shift
SBUF
Read
SBUF
Internal Bus
AI06846
Figure 34. Serial Port Mode 3, Waveforms
Tx Clock
Write to SBUF
S1P1
Send
Data
Transmit
Shift
Start Bit
D0
D1
D2
D3
D4
D5
D6
D7
TB8
TxD
TI
Stop Bit
Stop Bit
Generator
÷16 Reset
Rx Clock
Start Bit
D0
D1
D2
D3
D4
D5
D6
D7
RB8
RxD
Stop Bit
Receive
Bit Detector
Sample Times
Shift
RI
AI06847
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