UPSD3212C, UPSD3212CV
Table 17. PSD Module Register Address Offset
CSIOP
Addr
Offset
Bit Register Name
Reset
Value
Register Name
Comments
7
6
5
4
3
2
1
0
00
02
Data In (Port A)
Control (Port A)
Reads Port pins as input
Configure pin between I/O or Address Out Mode. Bit = 0 selects I/
O
00
04
06
Data Out (Port A)
Direction (Port A)
Latched data for output to Port pins, I/O Output Mode
Configures Port pin as input or output. Bit = 0 selects input
00
00
Configures Port pin between CMOS, Open Drain or Slew rate. Bit
= 0 selects CMOS
08
0A
0C
Drive (Port A)
00
Input Macrocell
(Port A)
Reads latched value on Input Macrocells
Enable Out
(Port A)
Reads the status of the output enable control to the Port pin driver.
Bit = 0 indicates pin is in input mode.
01
03
05
07
09
Data In (Port B)
Control (Port B)
Data Out (Port B)
Direction (Port B)
Drive (Port B)
00
00
00
00
Input Macrocell
(Port B)
0B
0D
Enable Out
(Port B)
10
12
14
16
Data In (Port C)
Data Out (Port C)
Direction (Port C)
Drive (Port C)
00
00
00
Input Macrocell
(Port C)
18
1A
11
Enable Out
(Port C)
Only Bit 1 and
2 are used
Data In (Port D)
Data Out (Port D)
Direction (Port D)
Drive (Port D)
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
Only Bit 1 and
2 are used
13
15
17
1B
20
00
00
00
Only Bit 1 and
2 are used
Only Bit 1 and
2 are used
Enable Out
(Port D)
Only Bit 1 and
2 are used
Output
Macrocells AB
36/152
STMICROELECTRONICS [ ST ]
