UPSD3212C, UPSD3212CV
CSIOP
Addr
Offset
Bit Register Name
Reset
Register Name
Comments
Value
7
6
5
4
3
2
1
0
Output
Macrocells BC
21
22
23
C0
Mask Macrocells
AB
Mask Macrocells
BC
Primary Flash
Protection
Sec3_ Sec2_ Sec1_ Sec0_
Bit = 1 sector
is protected
Prot
Prot
Prot
Prot
Security Bit =
1 device is
secured
Secondary Flash Security
Sec1_ Sec0_
C2
B0
*
*
*
*
*
*
Protection
_Bit
Prot
Prot
*
PLD
Mcells array-
clk
PLD
Control PLD
power
consumption
PLD
Turbo
APD
PMMR0
*
*
00
enable
clk
PLD
PLD
PLD
PLD
Blocking
inputs to PLD
array
B4
E0
PMMR2
Page
*
array array array array
Ale
*
*
00
00
Cntl2 Cntl1 Cntl0
Page Register
Configure
8032 Program
and Data
Periph-
mode
FL_ Boot_ FL_
Boot_
code
SR_
code
E2
VM
*
*
data
data code
Space
Note: (Register address = csiop address + address offset; where csiop address is defined by user in PSDsoft)
* indicates bit is not used and need to set to '0.'
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STMICROELECTRONICS [ ST ]
