UPSD3212C, UPSD3212CV
Figure 65. External Program Memory READ Cycle
t
t
LLPL
LHLL
ALE
t
t
AVLL
PLPH
t
LLIV
t
PLIV
PSEN
t
t
PXAV
LLAX
t
PXIZ
t
AZPL
PORT 0
INSTR
IN
A0-A7
A0-A7
t
AVIV
t
PXIX
A8-A11
A8-A11
PORT 2
AI06848
Table 91. External Program Memory AC Characteristics (with the 5V MCU Module)
Variable Oscillator
40MHz Oscillator
1/t
= 24 to 40MHz
CLCL
(1)
Symbol
Unit
Parameter
Min
35
Max
Min
– 15
CLCL
Max
t
2t
t
ALE pulse width
ns
ns
ns
ns
ns
ns
ns
ns
LHLL
AVLL
LLAX
LLIV
t
t
t
t
t
t
t
– 15
– 15
Address set up to ALE
Address hold after ALE
10
CLCL
CLCL
t
10
4t
– 45
ALE Low to valid instruction in
ALE to PSEN
55
CLCL
t
– 15
– 15
10
60
LLPL
PLPH
PLIV
PXIX
CLCL
3t
PSEN pulse width
CLCL
3t
t
– 45
– 10
PSEN to valid instruction in
Input instruction hold after PSEN
30
15
CLCL
0
0
(2)
Input instruction float after PSEN
ns
t
CLCL
PXIZ
(2)
t
– 5
Address valid after PSEN
Address to valid instruction in
Address float to PSEN
20
–5
ns
ns
ns
t
t
t
CLCL
PXAV
5t
CLCL
– 55
70
AVIV
–5
AZPL
Note: 1. Conditions (in addition to those in Table 86, V = 4.5 to 5.5V): V = 0V; C for Port 0, ALE and PSEN output is 100pF; C for
CC
SS
L
L
other outputs is 80pF
2. Interfacing the uPSD321X Devices to devices with float times up to 20ns is permissible. This limited bus contention does not cause
any damage to Port 0 drivers.
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STMICROELECTRONICS [ ST ]
