UPSD3212C, UPSD3212CV
Table 88. AC Symbols for Timing
Signal Letters
Signal Behavior
A
C
D
I
Address
t
Time
Clock
L
Logic Level Low or ALE
Logic Level High
Valid
Input Data
Instruction
ALE
H
V
X
Z
L
No Longer a Valid Logic Level
Float
N
P
Q
R
W
B
M
RESET Input or Output
PSEN signal
Output Data
RD signal
WR signal
PW Pulse Width
V
STBY
Output
Output Macrocell
Example: t
Invalid.
– Time from Address Valid to ALE
AVLX
Figure 64. Switching Waveforms – Key
INPUTS
OUTPUTS
WAVEFORMS
STEADY INPUT
STEADY OUTPUT
MAY CHANGE FROM
HI TO LO
WILL BE CHANGING
FROM HI TO LO
MAY CHANGE FROM
LO TO HI
WILL BE CHANGING
LO TO HI
DON'T CARE
CHANGING, STATE
UNKNOWN
OUTPUTS ONLY
CENTER LINE IS
TRI-STATE
AI03102
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