TS5070 - TS5071
Figure 6: Delayed Data Timing (short frame mode)
SERIAL CONTROL PORT TIMING
Symbol
fCCLK
tWCH
tWCL
tRC
Parameter
Min.
Typ.
Max.
Unit
MHz
ns
Frequency of CCLK
2.048
Period of CCLK High (measured from VIH to VIH)
Period of CCLK Low (measured from VIL to VIL)
Rise Time of CCLK (measured from VIL to VIH)
Fall Time of CCLK (measured from VIH to VIL)
Hold Time, CCLK Low to CS Low (CCLK1)
Hold Time, CCLK Low to CS High (CCLK8)
Setup Time, CS Transition to CCLK Low
160
160
ns
50
50
ns
tFC
ns
tHCS
10
100
70
ns
tHSC
ns
tSSC
ns
tSSCO
Setup Time, CS Transition to CCLK High (to insure CO is not
enabled for single byte)
50
ns
tSDC
tHCD
tDCD
Setup Time, CI (CI/O) Data in to CCLK low
Hold Time, CCLK Low to CI (CI/O) Invalid
50
ns
ns
ns
50
Delay Time, CCLK High to CO (CI/O) Data Out Valid
(load = 100 pF plus 2 LSTTL loads)
80
80
80
tDSD
tDDZ
Delay Time, CS Low to CO (CI/O) Valid
(applies only if separate CS used for byte 2)
ns
ns
Delay Time, CS or CCLK9 High to CO (CI/O) High Impedance
(applies to earlier of CS high or CCLK9 high)
15
INTERFACE LATCH TIMING
Symbol
Parameter
Min.
100
50
Typ.
Typ.
Max.
200
Unit
ns
tSLC
tHCL
tDCL
Setup Time, IL Valid to CCLK 8 of Byte 1 Low. IL as Input
Hold Time, IL Valid from CCLK 8 of Byte 1 Low. IL as Input
Delay Time, CCLK 8 of Byte 2 Low to IL. CL = 50 pF. IL as Output
ns
ns
MASTER RESET PIN
Symbol
Parameter
Duration of Master Reset High
Min.
Max.
Unit
tWMR
1
µs
20/32
STMICROELECTRONICS [ ST ]
