TS5070 - TS5071
TIMING SPECIFICATIONS (continued)
PCM INTERFACE TIMING
Symbol
Parameter
Min.
64
Typ.
Max.
4096
Unit
fBCLK
Frequency of BCLK (may vary from 64KHz to 4.096MHz in 8KHz
increments, TS5070 only)
kHz
tWBH
tWBL
tRB
Period of BCLK High (measured from VIH to VIH)
Period of BCLK Low (measured from VIL to VIL)
Rise Time of BCLK (measured from VIL to VIH)
Fall Time of BCLK (measured from VIH to VIL)
Hold Time, BCLK Low to FSX/R High or Low
Setup Time FSX/R High to BCLK Low
80
80
ns
ns
ns
ns
ns
ns
ns
30
30
tFB
tHBF
tSFB
tDBD
30
30
Delay Time, BCLK High to Data Valid (load = 100pF plus 2 LSTTL
loads)
80
tDBZ
Delay Time from BCLK8 Low to Dx Disabled (if FSx already low);
FSx Low to Dx Disabled (if BCLK8 low);
BCLK9 High to Dx Disabled (if FSx still high)
15
80
ns
tDBT
tZBT
Delay Time from BCLK and FSx Both High to TSx Low (Load = 100pF
plus 2 LSTTL loads)
60
ns
ns
Delay Time from BCLK8 low to TSx Disabled (if FSx already low);
15
60
FSx Low to TSx Disabled
(if BCLK8 low);
BCLK9 High to TSx Disabled
(if FSx still high);
tDFD
Delay Time, FSx High to Data Valid (load = 100pF plus 2 LSTTL
loads, applies if FSx rises later than BCLK rising edge in non-
delayed data mode only)
80
ns
tSDB
tHBD
Setup Time, DR 0/1 Valid to BCLK Low
Hold Time, BCLK Low to DR0/1 Invalid
30
20
ns
ns
Figure 5: Non Delayed Data Timing (short frame mode)
19/32
STMICROELECTRONICS [ ST ]
