Electrical characteristics
STM8S003F3 STM8S003K3
3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z.
Figure 38. SPI timing diagram - slave mode and CPHA = 0
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Figure 39. SPI timing diagram - slave mode and CPHA = 1
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1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD.
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DocID018576 Rev 5
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