STM8S003F3 STM8S003K3
Electrical characteristics
Figure 37. Recommended reset pin protection
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SPI serial peripheral interface
9.3.8
Unless otherwise specified, the parameters given in Table 43 are derived from tests
performed under ambient temperature, f frequency and V supply voltage
MASTER
DD
conditions. t
= 1/f
.
MASTER
MASTER
Refer to I/O port characteristics for more details on the input/output alternate function
characteristics (NSS, SCK, MOSI, MISO).
Table 43. SPI characteristics
Symbol
Parameter
Conditions
Master mode
Slave mode
Min
Max
Unit
0
0
8
7
fSCK
1/tc(SCK)
SPI clock frequency
MHz
tr(SCK)
tf(SCK)
SPI clock rise and fall time Capacitive load: C = 30 pF
-
25
(1)
tsu(NSS)
NSS setup time
NSS hold time
Slave mode
Slave mode
4 x tMASTER
70
-
-
(1)
th(NSS)
(1)
tw(SCKH)
tw(SCKL)
SCK high and low time
Data input setup time
Master mode
tSCK/2 - 15
tSCK/2 + 15
(1)
(1)
Master mode
5
5
-
tsu(MI)
tsu(SI)
(1)
Slave mode
-
ns
(1)
Master mode
7
-
th(MI)
th(SI)
Data input hold time
(1)
Slave mode
10
-
-
(1)(2)
ta(SO)
Data output access time
Data output disable time
Data output valid time
Data output valid time
Slave mode
3 x tMASTER
(1)(3)
tdis(SO)
tv(SO)
tv(MO)
th(SO)
Slave mode
25
-
-
65
30
-
(1)
(1)
(1)
(1)
Slave mode (after enable edge)
Master mode (after enable edge)
Slave mode (after enable edge)
Master mode (after enable edge)
-
27
11
Data output hold time
th(MO)
-
1. Values based on design simulation and/or characterization results, and not tested in production.
2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data.
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