STM32F405xx, STM32F407xx
Electrical characteristics
Table 20. Typical and maximum current consumption in Run mode, code with data processing
(1)
running from Flash memory (ART accelerator enabled) or RAM
Typ
Max(2)
Symbol
Parameter
Conditions
fHCLK
Unit
TA =
TA =
TA =
25 °C
85 °C 105 °C
168 MHz
144 MHz
120 MHz
90 MHz
60 MHz
30 MHz
25 MHz
16 MHz(6)
8 MHz
87
67
56
44
30
16
12
9
102
80
69
56
42
28
24
20
17
15
14
54
43
38
32
26
20
18
16
15
14
14
109
86
75
62
49
35
31
28
24
22
21
61
50
45
39
33
27
25
24
22
21
21
External clock(3), all
peripherals enabled(4)(5)
5
4 MHz
3
2 MHz
2
Supply current in
Run mode
IDD
mA
168 MHz
144 MHz
120 MHz
90 MHz
60 MHz
30 MHz
25 MHz
16 MHz(6)
8 MHz
40
31
26
20
14
8
External clock(3), all
peripherals disabled(4)(5)
6
5
3
4 MHz
2
2 MHz
2
1. Code and data processing running from SRAM1 using boot pins.
2. Based on characterization, tested in production at VDD max and fHCLK max with peripherals enabled.
3. External clock is 4 MHz and PLL is on when fHCLK > 25 MHz.
4. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.6 mA per ADC for
the analog part.
5. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption
should be considered.
6. In this case HCLK = system clock/2.
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