STM32F405xx, STM32F407xx
Electrical characteristics
Table 22. Typical and maximum current consumption in Sleep mode
Typ
Max(1)
Symbol
Parameter
Conditions
fHCLK
Unit
TA =
TA =
TA =
25 °C
85 °C
105 °C
168 MHz
144 MHz
120 MHz
90 MHz
60 MHz
30 MHz
25 MHz
16 MHz
8 MHz
59
46
38
30
20
11
8
77
61
53
44
34
24
21
18
16
15
14
27
22
20
19
17
16
15
14
14
13
13
84
67
60
51
41
31
28
25
23
22
21
35
29
28
26
24
23
22
21
21
21
21
External clock(2)
,
all peripherals enabled(3)
6
3
4 MHz
2
2 MHz
2
Supply current in
Sleep mode
IDD
mA
168 MHz
144 MHz
120 MHz
90 MHz
60 MHz
30 MHz
25 MHz
16 MHz
8 MHz
12
9
8
7
5
External clock(2), all
peripherals disabled
3
2
2
1
4 MHz
1
2 MHz
1
1. Based on characterization, tested in production at VDD max and fHCLK max with peripherals enabled.
2. External clock is 4 MHz and PLL is on when fHCLK > 25 MHz.
3. Add an additional power consumption of 1.6 mA per ADC for the analog part. In applications, this consumption occurs only
while the ADC is ON (ADON bit is set in the ADC_CR2 register).
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