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STM32F405RG 参数 Datasheet PDF下载

STM32F405RG图片预览
型号: STM32F405RG
PDF下载: 下载PDF文件 查看货源
内容描述: ARM的Cortex- M4 32B MCUFPU , 210DMIPS ,高达1MB闪存/ 1924KB RAM , USB OTG HS / FS [ARM Cortex-M4 32b MCUFPU, 210DMIPS, up to 1MB Flash/1924KB RAM, USB OTG HS/FS]
分类和应用: 闪存
文件页数/大小: 185 页 / 5432 K
品牌: STMICROELECTRONICS [ ST ]
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STM32F405xx, STM32F407xx  
Description  
has a typical frequency of 32 kHz. The RTC can be calibrated using an external 512 Hz  
output to compensate for any natural quartz deviation.  
Two alarm registers are used to generate an alarm at a specific time and calendar fields can  
be independently masked for alarm comparison. To generate a periodic interrupt, a 16-bit  
programmable binary auto-reload downcounter with programmable resolution is available  
and allows automatic wakeup and periodic alarms from every 120 µs to every 36 hours.  
A 20-bit prescaler is used for the time base clock. It is by default configured to generate a  
time base of 1 second from a clock at 32.768 kHz.  
The 4-Kbyte backup SRAM is an EEPROM-like memory area. It can be used to store data  
which need to be retained in V  
and standby mode. This memory area is disabled by  
BAT  
default to minimize power consumption (see Section 2.2.19: Low-power modes). It can be  
enabled by software.  
The backup registers are 32-bit registers used to store 80 bytes of user application data  
when V power is not present. Backup registers are not reset by a system, a power reset,  
DD  
or when the device wakes up from the Standby mode (see Section 2.2.19: Low-power  
modes).  
Additional 32-bit registers contain the programmable alarm subseconds, seconds, minutes,  
hours, day, and date.  
Like backup SRAM, the RTC and backup registers are supplied through a switch that is  
powered either from the V supply when present or from the V  
pin.  
DD  
BAT  
2.2.19  
Low-power modes  
The STM32F405xx and STM32F407xx support three low-power modes to achieve the best  
compromise between low power consumption, short startup time and available wakeup  
sources:  
Sleep mode  
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can  
wake up the CPU when an interrupt/event occurs.  
Stop mode  
The Stop mode achieves the lowest power consumption while retaining the contents of  
SRAM and registers. All clocks in the V domain are stopped, the PLL, the HSI RC  
12  
and the HSE crystal oscillators are disabled. The voltage regulator can also be put  
either in normal or in low-power mode.  
The device can be woken up from the Stop mode by any of the EXTI line (the EXTI line  
source can be one of the 16 external lines, the PVD output, the RTC alarm / wakeup /  
tamper / time stamp events, the USB OTG FS/HS wakeup or the Ethernet wakeup).  
Standby mode  
The Standby mode is used to achieve the lowest power consumption. The internal  
voltage regulator is switched off so that the entire V domain is powered off. The PLL,  
12  
the HSI RC and the HSE crystal oscillators are also switched off. After entering  
DocID022152 Rev 4  
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