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ST92F150JDV1Q6 参数 Datasheet PDF下载

ST92F150JDV1Q6图片预览
型号: ST92F150JDV1Q6
PDF下载: 下载PDF文件 查看货源
内容描述: 8月16日- BIT单电压闪存单片机系列内存, E3 TMEMULATED EEPROM , CAN 2.0B和J1850 BLPD [8/16-BIT SINGLE VOLTAGE FLASH MCU FAMILY WITH RAM, E3 TMEMULATED EEPROM, CAN 2.0B AND J1850 BLPD]
分类和应用: 闪存微控制器和处理器外围集成电路光电二极管可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟
文件页数/大小: 426 页 / 3830 K
品牌: STMICROELECTRONICS [ ST ]
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ST92F124/F150/F250 - ELECTRICAL CHARACTERISTICS  
EMC CHARACTERISTICS (Cont’d)  
Absolute Maximum Ratings (Electrical Sensi-  
tivity)  
Electro-Static Discharge (ESD)  
Electro-Static Discharges (a positive then a nega-  
tive pulse separated by 1 second) are applied to  
the pins of each sample according to each pin  
combination. The sample size depends on the  
number of supply pins in the device (3 parts*(n+1)  
supply pin). Two models can be simulated: Human  
Body Model and Machine Model. This test con-  
forms to the JESD22-A114A/A115A standard.  
Based on three different tests (ESD, LU and DLU)  
using specific measurement methods, the product  
is stressed in order to determine its performance in  
terms of electrical sensitivity. For more details, re-  
fer to the application note AN1181.  
Absolute Maximum Ratings  
1)  
Symbol  
Ratings  
Conditions  
Maximum value  
Unit  
Electro-static discharge voltage  
(Human Body Model)  
T =+25°C  
V
2000  
A
ESD(HBM)  
V
Electro-static discharge voltage  
(Machine Model)  
T =+25°C  
V
200  
A
ESD(MM)  
Notes:  
1. Data based on characterization results, not tested in production.  
Static and Dynamic Latch-Up  
LU: 3 complementary static tests are required  
on 10 parts to assess the latch-up performance.  
A supply overvoltage (applied to each power  
supply pin) and a current injection (applied to  
each input, output and configurable I/O pin) are  
performed on each sample. This test conforms  
to the EIA/JESD 78 IC latch-up standard. For  
more details, refer to the application note  
AN1181.  
DLU: Electro-Static Discharges (one positive  
then one negative test) are applied to each pin  
of 3 samples when the micro is running to  
assess the latch-up performance in dynamic  
mode. Power supplies are set to the typical  
values, the oscillator is connected as near as  
possible to the pins of the micro and the  
component is put in reset mode. This test  
conforms to the IEC1000-4-2 and SAEJ1752/3  
standards. For more details, refer to the  
application note AN1181.  
Electrical Sensitivities  
1)  
Symbol  
Parameter  
Static latch-up class  
Dynamic latch-up class  
Conditions  
Class  
T =+25°C  
A
A
A
A
LU  
T =+85°C  
A
T =+125°C  
A
V
=5.5V, f  
=4MHz, T =+25°C  
OSC A  
DLU  
A
DD  
Notes:  
1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC spec-  
ifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B Class strictly covers all the  
JEDEC criteria (international standard).  
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