10-BIT ANALOG TO DIGITAL CONVERTER (ADC)
REGISTER DESCRIPTION (Cont’d)
Bit 4 = EXTG: External Trigger Enable.
This bit is set and cleared by software.
0: External trigger disabled.
1: External trigger enabled. Allows a conversion
sequence to be started on the subsequent edge
of the external signal applied to the EXTRG pin
(when enabled as an Alternate Function).
Bit 0 = ST: Start/Stop.
0: Stop conversion. When the ADC converter is
running in Single Mode, this bit is hardware re-
set at the end of a sequence of conversions.
1: Start a sequence of conversions.
Note: If a write access to this register occurs, the
conversion is re-started from the SC[3:0] channel.
Bit 3 = INTG: Internal Trigger Enable.
This bit is set and cleared by software.
0: Internal trigger disabled.
INTERRUPT CONTROL REGISTER (AD_ICR)
1: Internal trigger enabled. Allows a conversion se-
quence to be started, synchronized by an inter-
nal signal (On-chip Event signal) from a Multi-
function Timer peripheral.
The Interrupt Control Register contains the three
priority level bits, the two source flags, and their bit
mask:
INTERRUPT CONTROL REGISTER (AD_ICR)
R254 - Read/Write
Register Page: 63
Reset Value: 0000 0111 (07h)
Both External and Internal Trigger inputs are inter-
nally ORed, thus avoiding Hardware conflicts;
however, the correct procedure is to enable only
one alternate synchronization input at a time.
7
0
Note: The effect of either synchronization mode is
to set the START/STOP bit, which is reset by hard-
ware when in SINGLE mode, at the end of each
sequence of conversions.
ECV AWD ECI AWDI
X
PL2 PL1 PL0
Requirements: The External Synchronisation In-
put must receive a low level pulse wider than an
INTCLK period and, for both External and On-Chip
Event synchronisation, the repetition period must
be greater than the time required for the selected
sequence of conversions.
Bit 7 = ECV: End of Conversion.
This bit is automatically set by hardware after a
group of conversions is completed. It must be re-
set by the user, before returning from the Interrupt
Service Routine. Setting this bit by software will
cause a software interrupt request to be generat-
ed.
0: No End of Conversion event occurred
1: An End of Conversion event occurred
Bit 2 = POW: Power Up/Power Down.
This bit is set and cleared by software.
0: Power down mode: all power-consuming logic is
disabled, thus selecting a low power idle mode.
1: Power up mode: the ADC converter logic and
analog circuitry is enabled.
Bit 6 = AWD: Analog Watchdog.
This is automatically set by hardware whenever ei-
ther of the two monitored analog inputs exceeds a
threshold. The threshold values are stored in reg-
isters R244/R245 and R248/R249 for channel A,
and in registers R246/R247 and R250/R251 for
channel B respectively. The Compare Result Reg-
ister (CRR) keeps track of the analog inputs ex-
ceeding the thresholds.
Bit 1 = CONT: Continuous/Single.
0: Single Mode: a single sequence of conversions
is initiated whenever an external (or internal)
trigger occurs, or when the ST bit is set by soft-
ware.
The AWD bit must be reset by the user, before re-
turning from the Interrupt Service Routine. Setting
this bit by software will cause a software interrupt
request to be generated.
0: No Analog Watchdog event occurred
1: An Analog Watchdog event occurred
1: Continuous Mode: the first sequence of conver-
sions is started, either by software (by setting
the ST bit), or by hardware (on an internal or ex-
ternal trigger, depending on the setting of the
INTG and EXTG bits); a continuous conversion
sequence is then initiated.
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STMICROELECTRONICS [ ST ]
