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ST92F150JDV1Q6 参数 Datasheet PDF下载

ST92F150JDV1Q6图片预览
型号: ST92F150JDV1Q6
PDF下载: 下载PDF文件 查看货源
内容描述: 8月16日- BIT单电压闪存单片机系列内存, E3 TMEMULATED EEPROM , CAN 2.0B和J1850 BLPD [8/16-BIT SINGLE VOLTAGE FLASH MCU FAMILY WITH RAM, E3 TMEMULATED EEPROM, CAN 2.0B AND J1850 BLPD]
分类和应用: 闪存微控制器和处理器外围集成电路光电二极管可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟
文件页数/大小: 426 页 / 3830 K
品牌: STMICROELECTRONICS [ ST ]
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10-BIT ANALOG TO DIGITAL CONVERTER (ADC)  
Table 68. Compare Channels definition  
REGISTER DESCRIPTION (Cont’d)  
CONTROL LOGIC REGISTER 1 (CLR1)  
R252 - Read/Write  
Register Page: 63  
Reset Value: 0000 1111 (0Fh)  
CC[3:0]  
Channel A  
Channel B  
0100  
0101  
0110  
0111  
1000  
1001  
1010  
1011  
1100  
1101  
1110  
1111  
3
4
5
6
7
4
5
6
7
8
7
0
SC3 SC2 SC1 SC0 CC3 CC2 CC1 CC0  
Bits 7:4 = SC[3:0]: Start Conversion Channel  
These four bits define the starting analog input  
channel (Autoscan Mode). The first channel ad-  
dressed by SC[3:0] is converted, then the channel  
number is incremented for the successive conver-  
sion, until channel 15 (1111) is converted. When  
SC3, SC2, SC1 and SC0 are all set, only channel  
15 will be converted.  
8
9
9
10  
11  
12  
13  
14  
15  
10  
11  
12  
13  
14  
Bits 3:0 = CC[3:0]: Compare Channels  
The programmed value corresponds to the first of  
the two adjacent channels (A) on which it is possi-  
ble to define a level window for the converted ana-  
log input (see Table 68).  
CONTROL LOGIC REGISTER 2 (CLR2)  
R253 - Read/Write  
Register Page: 63  
Reset Value: 1010 0000 (A0h)  
Note: If a write access to this register occurs, the  
conversion is re-started from the SC[3:0] channel.  
7
0
PR2 PR1 PR0 EXTG INTG POW CONT ST  
Table 68. Compare Channels definition  
CC[3:0]  
Channel A  
Channel B  
Bits 7:5 = PR[2:0]: INTCLK Frequency Prescaler  
These bits determine the ratio between the ADC  
clock and the system clock (INTCLK) according to  
Table 69.  
0000  
0001  
0010  
0011  
15  
0
1
0
1
2
3
2
Table 69. Prescaler programming  
T
f
T
f
T
T
f
T
T
Conv  
ADC  
Sample  
ADC  
Sample  
Conv  
ADC  
Sample Conv  
T
/
A/D clock  
(µs)  
(MHz)  
(µs)  
(MHz)  
(µs)  
(µs)  
(MHz)  
(µs)  
(µs)  
PR[2:0]  
T
INTCLK  
@T  
= 8MHz  
@T  
= 20MHz  
@T  
=24MHz  
INTCLK  
INTCLK  
INTCLK  
000  
001  
010  
011  
100  
101  
110  
111  
2
4
6
4.00  
2.00  
1.33  
1.00  
0.80  
0.66  
0.57  
0.50  
2
4
6
8
7
10.00  
5.00  
3.33  
2.50  
2.00  
1.66  
1.43  
1.25  
Not Allowed  
Not Allowed  
12.00  
6.00  
4.00  
3.00  
2.40  
2.00  
1.71  
1.50  
Not Allowed  
Not Allowed  
14  
21  
28  
2.4  
3.2  
4
8.4  
11.2  
14  
2
7
8
2.66  
9.33  
10  
12  
14  
16  
Not Allowed  
Not Allowed  
Not Allowed  
Not Allowed  
3.33 11.66  
14  
4.8  
5.6  
6.4  
16.8  
19.6  
22.4  
4
4.66 16.33  
5.33 18.66  
371/426  
9
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