CONTROLLER AREA NETWORK (bxCAN)
CONTROLLER AREA NETWORK (Cont’d)
– The transmit interrupt can be generated by the
following events:
– The error and status change interrupt can be
generated by the following events:
– Transmit mailbox 0 becomes empty, RQCP0
bit in the CTSR register set.
– Error condition, for more details on error con-
ditions please refer to the CAN Error Status
register (CESR).
– Transmit mailbox 1 becomes empty, RQCP1
bit in the CTSR register set.
– Wake-up condition, SOF monitored on the
CAN Rx signal.
– Transmit mailbox 2 becomes empty, RQCP2
bit in the CTSR register set.
– The FIFO 0 interrupt can be generated by the
10.10.7 Register Access Protection
following events:
Erroneous access to certain configuration regis-
ters can cause the hardware to temporarily disturb
the whole CAN network. Therefore the following
registers can be modified by software only while
the hardware is in initialization mode:
– Reception of a new message, FMP bits in the
CRFR0 register incremented.
– FIFO0 full condition, FULL bit in the CRFR0
register set.
CBTR0, CBTR1, CFCR0, CFCR1, CFMR and
CDGR registers.
– FIFO0 overrun condition, FOVR bit in the
CRFR0 register set.
Although the transmission of incorrect data will not
cause problems at the CAN network level, it can
severely disturb the application. A transmit mail-
box can be only modified by software while it is in
empty state, refer to Figure 147.Transmit Mailbox
States
– The FIFO 1 interrupt can be generated by the
following events:
– Reception of a new message, FMP bits in the
CRFR1 register incremented.
– FIFO1 full condition, FULL bit in the CRFR1
register set.
The filters must be deactivated before their value
can be modified by software. The modification of
the filter configuration (scale or mode) can be
done by software only in initialization mode.
– FIFO1 overrun condition, FOVR bit in the
CRFR1 register set.
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