J1850 Byte Level Protocol Decoder (JBLPD)
J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)
10.9.6.3 DMA Management in Reception Mode
through the DMA Address Register (or Register
pair);
The DMA in reception is performed when the
RDRF bit of the STATUS register is set (by hard-
ware). The RDRF bit is reset as soon as the DMA
cycle is finished.
To enable the DMA feature, the RXD_M bit of the
IMR register must be set (by software).
– A post-increment of the DMA Address Register
(or Register pair);
– A post-decrement of the DMA transaction coun-
ter, which contains the number of transactions
that have still to be performed.
Each DMA request performs the transfer of a sin-
gle byte from the RXDATA register of the peripher-
al toward Register File or Memory Space (Figure
139).
Note: When the REOBP pending bit is set (at the
end of the last DMA transfer), the reception DMA
enable bit (RXD_M) is automatically reset by hard-
ware. However, the DMA can be disabled by soft-
ware resetting the RXD_M bit.
Each DMA transfer consists of three operations
that are performed with minimum use of CPU time:
Note: The DMA request acknowledge could de-
pend on the priority level stored in the PRLR regis-
ter.
– A load from the JBLPD data register (RXDATA)
to a location of Register File/Memory addressed
Figure 139. DMA in Reception Mode
Register File
or
Memory space
Previous data
Data received
RXDATA
Current
Address
Pointer
JBLPD peripheral
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STMICROELECTRONICS [ ST ]
