ST92F124/F150/F250 - RESET AND CLOCK CONTROL UNIT (RCCU)
Figure 60. ST92F124/F150/F250 Clock Distribution Diagram
1...64
1...8
Baud Rate
Prescaler
Baud Rate
Generator
1/2
SCK
Master
CAN
ADC
1/N
1...8
3-bit Prescaler
N=2,4,16,32
1/2
SCK
Slave
(Max INTCLK/2)
LOGIC
SPI
1...128
1...256
N=2,4,8
1/N
1,3,4,13
EXTCLKx
(Max INTCLK/4)
EFTx
SCI-A
SCI-M
1...256
Baud Rate
Generator
1/N
1/3
N = 2...(216-1)
TxINA/TxINB
(Max INTCLK/3)
1...64
MFTx
WDG
1...256
1/4
JBLPD
WDIN
N=4,6,8...258
P6.5
STD
1/N
Fscl ≤100 kHz
1...256
FAST
Fscl > 100 kHz
Fscl ≤ 400 kHz
1/N
N=6,9,12...387
1/4
2
I C
1...8
3-bit Prescaler
STIM
CPUCLK
1/16
P4.1
P6.0
CPU
CLOCK2/8
1/8
CK_128
INTCLK
EMBEDDED MEMORY
CKAF_SEL
XT_DIV16
0
1
1/4
0
1
1/16
CSU_CKSEL
RAM
MX(1:0)
DIV2
EPROM
FLASH
0
1
PLL
x
0
1
CLOCK1
1/ N
3 TM
1/2
CLOCK2
E
6/8/10/14
DX(2:0)
CK_AF
P7.0
RCCU
126/426
9