ST92F124/F150/F250 - INTERRUPTS
WAKE-UP / INTERRUPT LINES MANAGEMENT UNIT (Cont’d)
WAKE-UP
TRIGGER
REGISTER
HIGH
WAKE-UP PENDING REGISTER HIGH
(WUPRH)
(WUTRH)
R252 - Read/Write
Register Page: 57
Reset Value: 0000 0000 (00h)
R254 - Read/Write
Register Page: 57
Reset Value: 0000 0000 (00h)
7
0
7
0
WUT15 WUT14 WUT13 WUT12 WUT11 WUT10 WUT9 WUT8
WUP15 WUP14 WUP13 WUP12 WUP11 WUP10 WUP9 WUP8
Bit 7:0 = WUT[15:8]: Wake-Up Trigger Polarity
Bits
These bits are set and cleared by software.
0: The corresponding WUPx pending bit will be set
on the falling edge of the input wake-up line .
1: The corresponding WUPx pending bit will be set
on the rising edge of the input wake-up line.
Bit 7:0 = WUP[15:8]: Wake-Up Pending Bits
These bits are set by hardware on occurrence of
the trigger event on the corresponding wake-up
line. They must be cleared by software. They can
be set by software to implement a software inter-
rupt.
0: No Wake-up Trigger event occurred
1: Wake-up Trigger event occured
WAKE-UP TRIGGER REGISTER LOW (WUTRL)
R253 - Read/Write
WAKE-UP PENDING REGISTER LOW (WUPRL)
R255 - Read/Write
Register Page: 57
Reset Value: 0000 0000 (00h)
Register Page: 57
7
0
Reset Value: 0000 0000 (00h)
7
0
WUT7 WUT6 WUT5 WUT4 WUT3 WUT2 WUT1 WUT0
WUP7 WUP6 WUP5 WUP4 WUP3 WUP2 WUP1 WUP0
Bit 7:0 = WUT[7:0]: Wake-Up Trigger Polarity Bits
These bits are set and cleared by software.
0: The corresponding WUPx pending bit will be set
on the falling edge of the input wake-up line.
1: The corresponding WUPx pending bit will be set
on the rising edge of the input wake-up line.
Bit 7:0 = WUP[7:0]: Wake-Up Pending Bits
These bits are set by hardware on occurrence of
the trigger event on the corresponding wake-up
line. They must be cleared by software. They can
be set by software to implement a software inter-
rupt.
WARNING
0: No Wake-up Trigger event occurred
1: Wake-up Trigger event occured
1. As the external wake-up lines are edge trig-
gered, no glitches must be generated on these
lines.
Note: To avoid losing a trigger event while clear-
ing the pending bits, it is recommended to use
read-modify-write instructions (AND, BRES,
BAND) to clear them.
2. If either a rising or a falling edge on the external
wake-up lines occurs while writing the
WUTRLH or WUTRL registers, the pending bit
will not be set.
5.12.6 Important Note On WUIMU
Refer to Section 13.1.2 on page 408.
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