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ST92F150JDV1Q6 参数 Datasheet PDF下载

ST92F150JDV1Q6图片预览
型号: ST92F150JDV1Q6
PDF下载: 下载PDF文件 查看货源
内容描述: 8月16日- BIT单电压闪存单片机系列内存, E3 TMEMULATED EEPROM , CAN 2.0B和J1850 BLPD [8/16-BIT SINGLE VOLTAGE FLASH MCU FAMILY WITH RAM, E3 TMEMULATED EEPROM, CAN 2.0B AND J1850 BLPD]
分类和应用: 闪存微控制器和处理器外围集成电路光电二极管可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟
文件页数/大小: 426 页 / 3830 K
品牌: STMICROELECTRONICS [ ST ]
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ST92F124/F150/F250 - ON-CHIP DIRECT MEMORY ACCESS (DMA)  
6 ON-CHIP DIRECT MEMORY ACCESS (DMA)  
6.1 INTRODUCTION  
6.2 DMA PRIORITY LEVELS  
The ST9 includes on-chip Direct Memory Access  
(DMA) in order to provide high-speed data transfer  
between peripherals and memory or Register File.  
Multi-channel DMA is fully supported by peripher-  
als having their own controller and DMA chan-  
nel(s). Each DMA channel transfers data to or  
from contiguous locations in the Register File, or in  
Memory. The maximum number of bytes that can  
be transferred per transaction by each DMA chan-  
nel is 222 with the Register File, or 65536 with  
Memory.  
The 8 priority levels used for interrupts are also  
used to prioritize the DMA requests, which are ar-  
bitrated in the same arbitration phase as interrupt  
requests. If the event occurrence requires a DMA  
transaction, this will take place at the end of the  
current instruction execution. When an interrupt  
and a DMA request occur simultaneously, on the  
same priority level, the DMA request is serviced  
before the interrupt.  
An interrupt priority request must be strictly higher  
than the CPL value in order to be acknowledged,  
whereas, for a DMA transaction request, it must be  
equal to or higher than the CPL value in order to  
be executed. Thus only DMA transaction requests  
can be acknowledged when the CPL=0.  
The DMA controller in the Peripheral uses an indi-  
rect addressing mechanism to DMA Pointers and  
Counter Registers stored in the Register File. This  
is the reason why the maximum number of trans-  
actions for the Register File is 222, since two Reg-  
isters are allocated for the Pointer and Counter.  
Register pairs are used for memory pointers and  
counters in order to offer the full 65536 byte and  
count capability.  
DMA requests do not modify the CPL value, since  
the DMA transaction is not interruptable.  
Figure 56. DMA Data Transfer  
REGISTER FILE  
REGISTER FILE  
OR  
MEMORY  
DF  
REGISTER FILE  
GROUP F  
PERIPHERAL  
PAGED  
COUNTER  
ADDRESS  
PERIPHERAL  
DATA  
REGISTERS  
0
COUNTER VALUE  
TRANSFERRED  
DATA  
START ADDRESS  
VR001834  
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