欢迎访问ic37.com |
会员登录 免费注册
发布采购

ST7538 参数 Datasheet PDF下载

ST7538图片预览
型号: ST7538
PDF下载: 下载PDF文件 查看货源
内容描述: 电力线FSK收发器 [POWER LINE FSK TRANSCEIVER]
分类和应用:
文件页数/大小: 30 页 / 266 K
品牌: STMICROELECTRONICS [ ST ]
 浏览型号ST7538的Datasheet PDF文件第12页浏览型号ST7538的Datasheet PDF文件第13页浏览型号ST7538的Datasheet PDF文件第14页浏览型号ST7538的Datasheet PDF文件第15页浏览型号ST7538的Datasheet PDF文件第17页浏览型号ST7538的Datasheet PDF文件第18页浏览型号ST7538的Datasheet PDF文件第19页浏览型号ST7538的Datasheet PDF文件第20页  
ST7538  
Carrier/Preamble Detection  
The Carrier/Preamble Block is a digital Frequency detector Circuit.  
It can be used to manage the MAINS access and to detect an incoming signal.  
Two are the possible setting:  
- Carrier Detection  
- Preamble Detection  
CARRIER DETECTION: The Carrier/Preamble detection Block notifies to the host controller the  
presence of a Carrier when it detects on the RAI Input a signal with an harmonic component close to  
the programmed Carrier Frequency. The CD_PD signal sensitivity is identical to the data reception  
sensitivity (1mVrms Typ. in Normal Sensitivity Mode).  
The CD_PD line is forced to a logic level low when a Carrier is detected.  
PREAMBLE DETECTION: The Carrier/Preamble detection Block notifies to the host controller the  
presence of a Carrier modulated at the Programmed Baud Rate for at least 4 Consecutive Symbols  
(“1010” or “0101” are the symbols sequences detected).  
CD_PD line is forced low till a Carrier signal is detected and PLL is in the lock-in range.  
To reinforce the effectiveness of the information given by CD_PD Block, a digital filtering is applied on  
Carrier or Preamble notification signal (See Control Register Paragraph). The Detection Time Bits in the  
Control Register define the filter performance. Increasing the Detection Time reduced the false  
notifications caused by noise on main line. The Digital filter adds a delay to CD_PD notification equal to  
the programmed Detection Time. When the carrier frequency disappears, CD_PD line is held low for a  
period equal to the detection time and then forced high.  
Figure 10. CD_PD Timing during RX  
T
T
CD  
DCD  
CD_PD  
RAI  
D03IN1418  
Figure 11. Receiving Path Block Diagram  
RXFO  
31  
Bit 3,4  
Bit 3,4  
Bit 0-2  
Bit 23  
MIXER  
3
8
32  
AGC  
RAI  
RxD  
Bit 3,4 &14-21  
PLL  
Low Pass  
Band Pass  
IF FILTER  
Band Pass  
Band Pass  
CHANNEL  
FILTER  
DIGITAL  
FILTER  
FSK  
DEMODULAOR  
PRE-FILTER  
CLR/T  
LOCAL  
OSC  
GAIN  
CONTROL  
Bit 9 & 10  
Bit 12 & 13  
Bit 0 -2  
CARRIER/  
PREAMBLE  
DETECTION  
1
9
Carrier Detection  
CD_PD  
BU  
Low Pass  
BAND  
IN  
USE  
D03IN1419  
16/30