ST7538
■ Automatic Level Control (ALC)
The Automatic Level Control Block (ALC) is a variable gain amplifier (with 32 non linear discrete steps)
controlled by two analog feed backs acting at the same time. The ALC gain range is 0dB to 30 dB and
the gain change is clocked at 5KHz. Each step increases or reduces the voltage of 1dB (Typ).
Two are the control loops acting to define the ALC gain:
- A Voltage Control loop
- A Current Control Loop
The Voltage control loop acts to keep the Peak-to-Peak Voltage constant on Vsense. The gain
adjustment is related to the result of a peak detection between the Voltage waveform on Vsense and
two internal Voltage references.
- If Vsense < VCL - VCL
The next gain level is increased by 1 step
No Gain Change
TH
HYST
- If VCL - VCL
< Vsense < VCL + VCL
TH
HYST
TH HYST
- If Vsense > VCL + VLC
The next gain level is decreased by 1 step
TH
HYST
The Current control loop acts to limit the maximum Peak Output current inside ATOP1 and ATOP2.
The current control loop acts through the voltage control loop decreasing the Output Peak-to-Peak
Amplitude to reduce the Current inside the Power Line Interface.
The current sensing is done by mirroring the current in the High side MOS of the Power Amplifier (not
dissipating current Sensing). The Output Current Limit (up to 400mApeak), is set by means of an
external resistor (R ) connected between CL and PAVss. The resistor converts the current sensed into
CL
a voltage signal. The Peak current sensing block works as the Output Voltage sensing Block:
- If V(CL) < CCL - CCL
Voltage Control Loop Acting
No Gain Change
TH
HYST
- If CCL - CCL
< V(CL) < CCL + CCL
TH
HYST
TH HYST
- If V(CL) > CCL + CLC
The next gain level is decreased by 1 step
TH
HYST
Figure 13 shows the typical connection of Current anVoltage control loops.
Figure 13. Voltage and Current Feedback external interconnection Example
VRPK
ATOP/ATO
Vsense
Vout
ALC
R1
VOLTAGE
LOOP
VCLHYST
VCLTH
5.6nF
R2
1.865V (Typ)
CL
CURRENT
LOOP
CCLHYST
RCL
100pF
AVss
CCLTH
D03IN1421
Voltage Control Loop Formula
R1 + R2
--------------------
R2
VRPK
(VCLTH ± VCLHYST)
18/30
STMICROELECTRONICS [ ST ]
