ST7538
Receiving Mode
The receive section is active when RxTx Pin =”1” and REG_DATA=0.
The input signal is read on RAI Pin using SGND as ground reference and then pre-filtered by a Band pass
Filter (+-10KHz). The Pre-Filter can be removed setting one bit in the Control Register. The Input Stage
features a wide dynamic range to receive Signal with a Very Low Signal to Noise Ratio. The Amplitude of
the applied waveform is automatically adapted by an Automatic Gain Control block (AGC) and then filtered
by a Narrow Band Band-Pass Filter centered around the Selected Channel Frequency (+-6K). The result-
ing signal is down-converted by a mixer using a sinewave generated by the FSK Modulator. Finally an
Intermediate Frequency Band Pass-Filter (IF Filter) improves the Signal to Noise ration before sending the
signal to the FSK demodulator. The FSK demodulator then send the signal to the RX Logic for final digital
filtering. Digital filtering Removes Noise spikes far from the BAUD rate frequency and Reduces the Signal
Jitter. RxD Line is forced at logic level “0” when neither mark or space frequencies are detected on RAI Pin.
Mark and Space Frequency in Receiving Mode must be distant at least BaudRate/2 to have a correct de-
modulation.
While ST7538 is in Receiving Mode (RxTx pin =”1”), the transmit circuitry, Power Line Interface included,
are turned off. This allows the device to achieve a very low current consumption (5 mA typ). In Receiving
mode ATOP2 pin is internally connected to PAVSS.
■ High Sensitivity Mode
It is possible to increase ST7538 Receiving Sensitivity setting to “1” the High Sensitivity Bit of Control
Register. This Function allows to increase the communication reliability when the ST7538 sensitivity is
the limiting factor.
■ Synchronization Recovery System (PLL)
ST7538 embeds a Clock Recovery System to feature a Synchronous data exchange with the Host
Controller.
The clock recovery system is realized by means of a second order PLL. Data on the data line (RxD) are
stable on CLR/T line rising edge (CLR/T Falling edge synchronized to RxD line transitions ± LOCK-IN
Range).
The PLL Lock-in and Lock-out Range is ±π/2. When the PLL is in the unlock condition, CLR/T and RxD
lines are forced to a low logic level.
When PLL is in unlock condition it is sensitive to RxD Rising and Falling Edges. The maximum number
of transition required to reach the lock-in condition is 5. When in lock-in condition the PLL is sensitive
only to RxD rising Edges to reduce the CLR/T Jitter.
ST7538 PLL is forced in the un-lock condition, when more than 32 equal symbols are received.
Figure 9.
CLR/T
RxD
D03IN1417
LOCK-IN RANGE
15/30
STMICROELECTRONICS [ ST ]
