ST7538
–
Synchronous mode.
St7538 allows to interface the host Controller using a four lines synchronous interface (RXD,TXD, CLR/T
&
RxTx
). ST7538 is always the master of the communication and provides the clock reference on CLR/T
line.
When ST7538 is in receiving mode an internal PLL recovers the clock reference. Data on RxD line are
stable on CLR/T rising Edge.
When ST7538 is in transmitting mode the clock reference is internally generated and data are read on TxD
line on CLR/T rising Edge.
If
RxTx
line is set to “1” & REG_DATA=”0” (Data Reception), ST7538 enters in an Idle State and CLR/T
line is forced Low. After Tcc time the modem starts providing received data on RxD line.
If
RxTx
line is set to “0” & REG_DATA=”0” (Data Transmission), ST7538 d in an Idle State and transmission
circuitry is switched on. (figure 3). After Tcc time the modem starts transmitting data present on TXD line
(figure 3) .
Figure 2.
Receiving Bit Synchronization
Transmitting Bit Synchronization
CLR/T
CLR/T
RxD
TxD
T
S
D03IN1416
T
H
Figure 3. Data Reception -> Data Transmission -> Data reception
T
CC
CLR_T
T
B
RXD
REG_DATA
T
CR
RxTx
T
S
T
H
BIT22
D03IN1402
T
CC
T
DS
T
DH
T
CR
TXD
BIT23
PACKET MODE (Only for Reception)
In Packet mode data transmission from ST7538 to Host Controller is done at a higher speed than the
Mains one. This function could reduce the efficiency of data exchange process because the Host Control-
ler is involved in data reception for a shorter period of time.
To achieve this function is enabled an internal auxiliary buffer which stores the incoming bits. The buffer
is transferred to the host controller when full at the packet rate. The packet rate is programmable and is
related to the Mclk clock frequency. The length of the packet can be also programmed through the control
register (see table 9) to be 16, 14, 9 or 8 bits.
The packet mode to start working needs two levels of enable. One at the control register level the other at
the pin level. TxD is the pin that if forced High enables the Packet Mode Function. According to when TxD
is forced high, the next incoming bit is stored inside the internal buffer or delivered on RxD pin. If TxD pin
is forced low during a RX session the transceiver starts working in bit mode and the content of the packet
buffer is deleted.
12/30
STMICROELECTRONICS [ STMICROELECTRONICS ]
