5 System configuration
5.3.3
ST40RA I/O device interrupt allocation
INTEVT
code
0x1000
0 to 15
Reserved
Reserved
EMPI
INV_ADDR
Reserved
0x1380
0 to 15
0 to 15
0
0
INTPRI04[27:24]
INTPRI04[31:28]
0
INTPRI04[0:3]
ST40RA
Interrupt priority
Value
Initial value
Interrupt source
IPR
bit numbers
Priority
within IPR
setting unit
High to low
High to low
High to low
Mailbox
MAILBOX
Table 5: Mailbox and EMPI interrupt allocation
5.4
GPDMA channel mapping
For full details of the GPDMA controller see
ST40 System Architecture Manual Volume 1: System.
The ST40RA general purpose DMA controller channel map is shown in
Table 6.
Request
number
0
1
Associated
device
External device 0
External device 1
Protocol
DREQ or
DREQ/DRACK
DREQ or
DREQ/DRACK
Comment
The following pins are available for external peripherals:
DREQ[0:1],
DACK[0:1],
DRAK[0:1].
2 and 3
4
5
6
7
8
9 and 10
11
12
13
14
15 to 31
Reserved
SCIF1 transmit
SCIF1 received
SCIF2 transmit
SCIF2 receive
TMU
Reserved
PCI1
PCI2
PCI3
PCI4
Reserved
DREQ or
DREQ/DRACK
DREQ or
DREQ/DRACK
DREQ or
DREQ/DRACK
DREQ or
DREQ/DRACK
DREQ
DREQ
DREQ
DREQ
DREQ/DRACK
Typically used to trigger or pace memory transfers.
This allow SCIF to memory and memory to SCIF transfer
to be supported on any DMA channel.
May be used to improve the efficiency of transfers to and
from the PCI.
Table 6: GPDMA request number allocation
17/94
STMicroelectronics
ADCS 7260755H
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