5 System configuration
ST40RA
5.3
Interrupt mapping
For full details on the interrupt controller see
ST40 System Architecture Manual Volume 1:System.
The mapping of the CPU interrupts is described in
Section 5.3.1, Section 5.3.2
and
Section 5.3.3.
Note:
Some INTEVT codes are shown as reserved in
Table 3
and therefore cannot be generated by this
device.
5.3.1
ST40 core interrupt allocation
The allocation of core interrupts is as shown in
Table 3.
Interrupt priority
Value
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
15 to 0
15 to 0
15 to 0
15 to 0
15 to 0
15 to 0
0 to 15
0 to 15
TICPI2
0x460
Interrupt source
INTEVT
code
0x1C0
Initial value
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
13
10
7
4
0
0
0
0
IPR
bit numbers
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
IPRD[15:12]
IPRD[11:8]
IPRD[7:4]
IPRD[3:0]
IPRC[3:0]
IPRA[15:12]
IPRA[11:8]
IPRA[7:4]
Priority
within IPR
setting unit
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
High
Low
NMI
IRL
level
encoding
IRL3–IRL0 = F
IRL3–IRL0
=
E
IRL3–IRL0
=
D
IRL3–IRL0
=
C
IRL3–IRL0
=
B
IRL3–IRL0
=
A
IRL3–IRL0
=
9
IRL3–IRL0
=
8
IRL3–IRL0
=
7
IRL3–IRL0
=
6
IRL3–IRL0
=
5
IRL3–IRL0
=
4
IRL3–IRL0
=
3
IRL3–IRL0
=
2
IRL3–IRL0
=
1
IRL
independent
encoding
IRL0
IRL1
IRL2
IRL3
H-UDI
TMU0
TMU1
TMU2
H-UDI
TUNI0
TUNI1
TUNI2
0x200
0x220
0x240
0x260
0x280
0x2A0
0x2C0
0x2E0
0x300
0x320
0x340
0x360
0x380
0x3A0
0x3C0
0x240
0x2A0
0x300
0x360
0x600
0x400
0x420
0x440
Table 3: ST40 core interrupt allocation (page 1 of 2)
15/94
STMicroelectronics
ADCS 7260755H
STMICROELECTRONICS [ STMICROELECTRONICS ]
