5 System configuration
ST40RA
5.8
Memory bridge control
The architecture of the SuperHyway interconnect is shown in
Figure 3.
Initiators are shown on the
left, and targets are shown on the right of the interconnect. The bit width of the initiator and target
ports are shown in the diagram.
LMI
64
SH core
32
Memory
bridge
EMI
EMPI
Memory
bridge
32
32
PCI_ST_I
Memory
bridge
32
SuperHyway
Interconnect
32
Memory
bridge
PCI_ST_T
GPDMA
PER
32
32
SH_PER
P
I
Figure 3: ST40RA interconnect architecture
The ST40RA architecture requires seven memory bridges on clock change boundaries.
Memory bridge number
1
2
3
4
5
6
7
SuperHyway type
T3
T3
T1
T2
T2
T3
T3
Subsystem
EMI target
EMPI initiator
EMI_SS target
Reserved
Reserved
PCI_ST_I
PCI_ST_T
Table 9: Memory bridges
21/94
STMicroelectronics
ADCS 7260755H
STMICROELECTRONICS [ STMICROELECTRONICS ]
