ST40RA
5 System configuration
Interrupt source
INTEVT
code
0x480
0x4A0
0x4C0
0x4E0
0x500
Interrupt priority
Value
Initial value
IPR
bit numbers
Priority
within IPR
setting unit
High
RTC
ATI
PRI
CUI
0 to 15
0
IPRA [3:0]
to
low
SCIF1
ERI
RXI
BRI
TXI
High
0 to 15
0
IPRB[7:4]
to
low
0x520
0x540
0x700
0x720
0 to 15
0
IPRC[7:4]
0x740
0x760
0x560
0 to 15
0
IPRB[15:12]
SCIF2
ERI
RXI
BRI
TXI
High
to
low
WDT
ITI
-
Table 3: ST40 core interrupt allocation (page 2 of 2)
5.3.2
ST40 standard system interrupt allocation
Standard ST40 family interrupts are mapped as shown in
Table 4.
Interrupt priority
Value
Initial value
Priority
within IPR
setting unit
High to low
Interrupt source
INTEVT
code
0xA00
0xA20
0xA40
0xA60
IPR
bit numbers
PCI
PCI_SERR_INT
PCI_ERR_INT
PCI_AD_INT
PCI_PWR_DWN
Reserved
0 to 15
0
INTPRI00[0:3]
INTPRI00[7:4]
High
to
low
DMAC
DMA_INT0
DMA_INT1
DMA_INT2
DMA_INT3
DMA_INT4
Reserved
DMA_ERR
0xB00
0xB20
0xB40
0xB60
0xB80
0 to 15
0
INTPRI00[11:8]
High
to
low
0xBC0
0xC00
0xC80
0xD00
0 to 15
0 to 15
0 to 15
0
0
0
INTPRI00[15:12]
INTPRI00[19:16]
INTPRI00[23:20]
-
-
-
PIO0
PIO1
PIO2
PIO0
PIO1
PIO2
Table 4: ST40 standard interrupt allocation
ADCS 7260755H
STMicroelectronics
16/94
STMICROELECTRONICS [ STMICROELECTRONICS ]
